PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 39

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.11.3
2.11.3.1
status register when the master abort is received on the secondary interface. When master abort is
detected in posted write transaction with both master-abort-mode bit (bit[5] of bridge control
register) and the SERR# enable bit (bit 8 of command register for secondary bus) are set,
PI7C8154A asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-
posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C8154A performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort received
bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
TARGET TERMINATION RECEIVED BY PI7C8154A
When PI7C8154A initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types
of termination:
PI7C8154A handles these terminations in different ways, depending on the type of transaction
being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154A initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator.
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A