PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 29

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7.3
2.7.4
READ PREFETCH ADDRESS BOUNDARIES
PI7C8154A imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8154A stops pre-fetched data,
unless the target signals a target disconnect before the read prefetched boundary is reached. When
PI7C8154A finishes transferring this read data to the initiator, it returns a target disconnect with the
last data transfer, unless the initiator completes the transaction before all pre-fetched read data is
delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME#. Section 2.7.6 describes flow-through mode
during read operations.
Table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow-
through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5 READ TRANSACTION PREFETCHING
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
DELAYED READ REQUESTS
PI7C8154A treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
placed in the read data queue directed toward the initiator bus interface and is transferred to the
initiator when the initiator repeats the read transaction.
PI7C8154A accepts a delayed read request, by sampling the read address, read bus command, and
address parity. When IRDY# is asserted, PI7C8154A then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. PI7C8154A terminates
the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the
initiator is required to continue to repeat the same read transaction until at least one data transfer is
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
Page 29 of 112
Cache Line Size
(CLS)
CLS = 0 or 16
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 1, 2, 4, 8
Prefetch Aligned Address Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address boundary
Cache line address boundary
16-DWORD aligned address boundary
Cache line boundary
Queue full
Second cache line boundary
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A