PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 62

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
6.1
6.2
6.2.1
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most
of these events have additional device-specific disable bits in the P_SERR# event disable register
that make it possible to mask out P_SERR# assertion for specific events. The master timeout
condition has a SERR# enable bit for that event in the bridge control register and therefore does not
have a device-specific disable bit.
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a target for
transactions that cross the bridge.
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a locked
transaction crosses the bridge. A primary master can lock a primary target without affecting the
status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a
primary target at the same time that a secondary master locks a secondary target.
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154A
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked
transactions, the initiator must first check that both of the following conditions are met:
The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one
clock cycle later. Once a data transfer is completed from the target, the target lock has been
achieved.
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
Locked transactions can cross the bridge only in the downstream direction, from the primary bus to
the secondary bus.
When the target resides on another PCI bus, the master must acquire not only the lock on its own
PCI bus but also the lock on every bus between its bus and the target’s bus. When the bridge
detects on the primary bus, an initial locked transaction intended for a target on the secondary bus,
Target abort detected during posted write transaction.
Master abort detected during posted write transaction.
Posted write data discarded after 2
Parity error reported on target bus during posted write transaction (see previous section)
Delayed write data discarded after 2
Delayed read data cannot be transferred from target after 2
retries received)
Master timeout on delayed transaction
The PCI bus must be idle.
The LOCK# signal must be de-asserted.
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(default) attempts to deliver (2
(default) attempts to deliver (2
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(default) attempts (2
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
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target retries received).
target retries received)
PCI-to-PCI BRIDGE
Advance Information
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PI7C8154A
target