PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 54

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
5.2.1
5.2.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8154A attempts to pass the data parity condition from one
interface to the other unchanged, whenever possible, to allow the master and target devices to
handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that occurs
when a parity error is detected and the way in which the parity condition is forwarded across
PI7C8154A.
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION
SPACE
When PI7C8154A detects a data parity error during a Type 0 configuration write transaction to
PI7C8154A configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8154A asserts P_TRDY# and
writes the data to the configuration register. PI7C8154A also asserts P_PERR#. If the parity error
response bit is not set, PI7C8154A does not assert P_PERR#.
PI7C8154A sets the detected parity error bit in the status register, regardless of the state of the
parity error response bit.
READ TRANSACTIONS
When PI7C8154A detects a parity error during a read transaction, the target drives data and data
parity, and the initiator checks parity and conditionally asserts PERR#. For downstream
transactions, when PI7C8154A detects a read data parity error on the secondary bus, the following
events occur:
abort. If parity error response bit is not set, PI7C8154A proceeds normally and accepts
transaction if it is directed to or across PI7C8154A.
PI7C8154A sets the detected parity error bit in the secondary status register
PI7C8154A asserts P_SERR# and sets signaled system error bit in status register, if both of the
following conditions are met:
PI7C8154A asserts S_PERR# two cycles following the data transfer, if the secondary interface
parity error response bit is set in the bridge control register.
PI7C8154A sets the detected parity error bit in the secondary status register.
PI7C8154A sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8154A forwards the bad parity with the data back to the initiator on the primary bus. If
the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154A completes the transaction normally.
The SERR# enable bit is set in the command register
The parity error response bit is set in the bridge control register
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A