PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 76

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
CONFIGURATION REGISTERS
PCI configuration defines a 64 DWORD space to define various attributes of PI7C8154A as shown
below.
Table 14-1 CONFIGURATION SPACE MAP
Secondary
Preemptio
n Control
Arbiter
Secondary Latency
Bus
Chassis Number
Reserved
Reserved
Prefetchable Memory Limit Address
EEPROM Autoload Control/Status
Timer
31-24
Upstream (S to P) Memory Limit
Primary Master Timeout Counter
Power Management Capabilities
Data
I/O Limit Address Upper 16-bit
Hot Swap Control and Status
Upstream Memory Control
Memory Limit Address
Secondary Status
Arbiter Control
EEPROM Data
Bridge Control
Primary Status
Device ID
Reserved
VPD
PPB Support Extensions
GPIO Data and Control
Prefetchable Memory Limit Address Upper 32-bit
Prefetchable Memory Base Address Upper 32-bit
Upstream (S to P) Memory Limit Upper 32-bit
Upstream (S to P) Memory Base Upper 32-bit
Subordinate Bus
P_SERR# Status
Header Type
Slot Number
Class Code
Reserved
Number
23-16
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Hot Swap Switch Time Slot
VPD Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Secondary Bus Number
Primary Latency Timer
I/O Limit Address
Next Item Pointer
Next Item Pointer
Next Item Pointer
(not supported)
Interrupt Pin
Next Pointer
Prefetchable Memory Base Address
Secondary Master Timeout Counter
15-8
Upstream (S to P) Memory Base
I/O Base Address Upper 16-bit
EEPROM Address/Control
Diagnostic / Chip Control
Secondary Clock Control
Power Management Data
Extended Chip Control
Memory Base Address
Port Option
Vendor ID
Command
Reserved
ASYNCHRONOUS 2-PORT
Primary Bus Number
DEC 2009 REVISION 1.02
Capability Pointer
I/O Base Address
Cache Line Size
P_SERR# Event
(not supported)
Interrupt Line
Capability ID
Capability ID
Capability ID
Capability ID
Revision ID
Disable
PCI-to-PCI BRIDGE
7-0
Advance Information
PI7C8154A
C0h - CFh
D0h –D8h
6Ch - 70h
DWORD
Address
B4h –
84h –
ACh
DCh
0Ch
1Ch
3Ch
4Ch
7Ch
B0h
BFh
ECh
18h
2Ch
5Ch
E0h
E4h
E8h
00h
04h
08h
10h
14h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h
58h
60h
64h
68h
74h
78h
80h