PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 41

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.11.3.2
2.11.3.3
Table 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE
After the PI7C8154A makes 2
target bus, PI7C8154A asserts P_SERR# if the SERR# enable bit (bit 8 of command register for
the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-
delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C8154A will report system
error. See Section 5.4 for a description of system error conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8154A initiates a posted write transaction, the target termination cannot be passed back
to the initiator. Table 2-8 shows the response to each type of target termination that occurs during a
posted write transaction.
Table 2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
Note that when a target retry or target disconnect is returned and posted write data associated with
that transaction remains in the write buffers, PI7C8154A initiates another write transaction to
attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be
driven as for the initial write trans-action attempt. If a target disconnect is received, the address that
is driven on a subsequent write transaction attempt will be updated to reflect the address of the
current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a
partial delivery of write data to the target is performed before a target disconnect is received,
PI7C8154A will use the memory write command to deliver the rest of the write data. It is because
an incomplete cache line will be transferred in the subsequent write transaction attempt.
After the PI7C8154A makes 2
write data associated with that transaction, PI7C8154A asserts P_SERR# if the primary SERR#
enable bit is set (bit 8 of command register for secondary bus) and posted-write-non-delivery bit is
not set. The posted-write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset
64h). PI7C8154A will report system error. See Section 5.4 for a discussion of system error
conditions.
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C8154A initiates a delayed read transaction, the abnormal target responses can be passed
back to the initiator. Other target responses depend on how much data the initiator requests. Table
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Response
Returning disconnect to initiator with first data transfer only if multiple data phases
requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data phases
requested.
Returning target abort to initiator. Set received target abort bit in target interface status
register. Set signaled target abort bit in initiator interface status register.
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert P_SERR# if
enabled, and set the signaled-system-error bit in primary status register.
24
24
(default) attempts of the same delayed write trans-action on the
(default) write transaction attempts and fails to deliver all posted
Page 41 of 113
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A