PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 12

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1.1
1.2
1.2.1
SIGNAL DEFINITIONS
SIGNAL TYPES
SIGNALS
Note: Signal names that end with “#” are active LOW.
PRIMARY BUS INTERFACE SIGNALS
Signal Type
I
O
P
TS
STS
OD
Name
P_AD[31:0]
P_CBE[3:0]
P_PAR
P_FRAME#
Pin #
U2, U4, U1, V2, V1, V3,
W2, W1, W4, Y3, AA1,
AA3, Y4, AB3, AA4, Y5,
AB8, AA8, AC9, AB9,
AA9, AC10, AA10, Y11,
AB11, AA11, AA12, AB12,
AB13, AA13, Y13, AA14
Y2, AB4, AA7, AC11
AB7
AA5
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting.
Open Drain
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Type
STS
TS
TS
TS
Description
Primary Address / Data: Multiplexed address and
data bus. Address is indicated by P_FRAME#
assertion. Write data is stable and valid when
P_IRDY# is asserted and read data is stable and
valid when P_TRDY# is asserted. Data is
transferred on rising clock edges when both
P_IRDY# and P_TRDY# are asserted. During bus
idle, bridge drives P_AD[31:0] to a valid logic level
when P_GNT# is asserted.
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During
address phase, the initiator drives the transaction
type on these pins. After that, the initiator drives the
byte enables during data phases. During bus idle,
bridge drives P_CBE[3:0] to a valid logic level
when P_GNT# is asserted.
Primary Parity. P_PAR is even parity of
P_AD[31:0] and P_CBE[3:0] (i.e. an even number
of 1’s). P_PAR is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME#) for address parity. For write data
phases, P_PAR is valid one clock after P_IRDY# is
asserted. For read data phase, P_PAR is valid one
clock after P_TRDY# is asserted. Signal P_PAR is
tri-stated one cycle after the P_AD lines are tri-
stated. During bus idle, BRIDGE drives P_PAR to
a valid logic level when P_GNT# is asserted.
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning
and duration of an access. The de-assertion of
P_FRAME# indicates the final data phase requested
by the initiator. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A