PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 34

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.8.4
PI7C8154A also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. A Type 1 configuration command is
forwarded upstream when the following conditions are met:
The PI7C8154A forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Types 1 to Type 1 configuration write transactions are limited to a single data transfer.
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical
PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded
across the bridge. Special cycle transactions can be generated from Type 1 configuration write
transactions in either the upstream or the down-stream direction.
PI7C8154A initiates a special cycle on the target bus when a Type 1 configuration write transaction
is being detected on the initiating bus and the following conditions are met during the address
phase:
When PI7C8154A initiates the transaction on the target interface, the bus command is changed
from configuration write to special cycle. The address and data are for-warded unchanged. Devices
that use special cycles ignore the address and decode only the bus command. The data phase
contains the special cycle message. The transaction is forwarded as a delayed transaction, but in
this case the target response is not forwarded back (because special cycles result in a master abort).
Once the transaction is completed on the target bus, through detection of the master abort
condition, PI7C8154A responds with TRDY# to the next attempt of the con-figuration transaction
from the initiator. If more than one data transfer is requested, PI7C8154A responds with a target
disconnect operation during the first data phase.
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus
number register and the upper limit (inclusive) in the subordinate bus number register.
The bus command is a configuration read or write transaction.
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the secondary
bus number register and the upper limit (inclusive) in the subordinate bus number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in configuration
space for downstream forwarding or equal to the value in the primary bus number register in
configuration space for upstream forwarding.
The bus command on CBE is a configuration write command.
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A