PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 33

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.8.3
PI7C8154A asserts a unique address line based on the device number. These address lines may be
used as secondary bus IDSEL signals. The mapping of the address lines depends on the device
number in the Type 1 address bits P_AD[15:11]. Table 2-6 presents the mapping that PI7C8154A
uses.
Table 2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING
PI7C8154A can assert up to 16 unique address lines to be used as IDSEL signals for up to 16
devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical
loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However,
if device numbers greater than 16 are desired, some external method of generating IDSEL lines
must be used, and no upper address bits are then asserted. The configuration transaction is still
translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a
secondary device, the transaction ends in a master abort.
PI7C8154A forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit
data transfer.
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when
two or more levels of PCI-to-PCI bridges are used.
When PI7C8154A detects a Type 1 configuration transaction intended for a PCI bus downstream
from the secondary bus, PI7C8154A forwards the transaction unchanged to the secondary bus.
Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle
transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs
when the following conditions are met during the address phase:
Device Number
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h – 1Eh
1Fh
Decodes the device number and drives the bit pattern specified in Table 2-6 on S_AD[31:16]
for the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0.
Leaves unchanged the function number and register number fields.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01110
11111
P_AD[15:11]
01010
01011
01100
01101
01111
10000 – 11110
Page 33 of 112
Secondary IDSEL S_AD[31:16]
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
Generate special cycle (P_AD[7:2] = 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
S_AD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
PI7C8154A