PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 31

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7.7
2.8
transaction. In this case, PI7C8154A will start the master timeout timer. The remaining read data
will be discarded after the master timeout timer expires. To provide better latency, if there are any
other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data
will be discarded even though the master timeout timer has not expired.
PI7C8154A implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head of the
read data queue. The initial value of this timer is programmable through configuration transaction.
If the initiator does not repeat the read transaction and before the master timeout timer expires (2
default), PI7C8154A discards the read transaction and read data from its queues. PI7C8154A also
conditionally asserts P_SERR# (see Section 5.4).
PI7C8154A has the capability to post multiple delayed read requests, up to a maximum of four in
each direction. If an initiator starts a read transaction that matches the address and read command
of a read transaction that is already queued, the current read command is not posted as it is already
contained in the delayed transaction queue.
See Section 4 for a discussion of how delayed read transactions are ordered when crossing
PI7C8154A.
FAST BACK-TO-BACK TRANSACTIONS
PI7C8154A is capable of decoding fast back-to-back read transactions on both the primary and
secondary. Also, PI7C8154A cannot generate fast back-to-back read transactions on the secondary
or primary even though bit[23] of offset 3Ch is set to ‘1’ or bit[9] of offset 04h is set to ‘1’.
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a
configuration space that is accessed by configuration commands. All registers are accessible in
configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration space,
the PI7C8154A also forwards configuration transactions for device initialization in hierarchical
PCI systems, as well as for special cycle generation.
To support hierarchical PCI bus systems, two types of configuration transactions are specified:
Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest two bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI bus,
or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is
identified by the configuration command and the lowest two address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For
single-function devices, this value is not decoded. The addresses of Type 1 configuration
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A
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