PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 50

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
4.1
snoop bit in the command register in configuration space. Note that PI7C8154A claims VGA
palette write transactions by asserting DEVSEL# in VGA snoop mode.
When VGA snoop bit is set, PI7C8154A forwards downstream transactions within the 3C6h, 3C8h
and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA
compatibility mode previously described. Again, address bits [15:10] are not decoded, while
address bits [31:16] must be equal to 0, which means that these addresses are aliases every 1KB
throughout the first 64KB of I/O space.
Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8154A behaves in the same
way as if only the VGA mode bit were set.
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8154A complies with the ordering rules set forth
in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge. This chapter
describes the ordering rules that control transaction forwarding across PI7C8154A.
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing
PI7C8154A:
Posted write transactions, comprised of memory write and memory write and invalidate
transactions.
Posted write transactions complete at the source before they complete at the destination; that is,
data is written into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write
transactions.
Delayed write requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue. A delayed write transaction must complete on the target bus before it
completes on the initiator bus.
Delayed write completion transactions, comprised of I/O write and configuration write
transactions.
Delayed write completion transactions complete on the target bus, and the target response is queued
in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the
original delayed write request; that is, a delayed write completion transaction proceeds from the
target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and
configuration read transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, &
configuration read transactions.
Delayed read completion transactions complete on the target bus, and the read data is queued in the
read data buffers. A delayed read completion transaction proceeds in the direction opposite that of
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A