PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 71

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2
9.3
9.4
EEPROM MODE AT RESET
During a reset, the bridge will autoload information/data from the EEPROM if the automatic load
condition is met. The first offset in the EEPROM contains a signature. If the signature is
recognized, the autoload will initiate right after the reset.
During the autoload, the bridge will read sequential words from the EEPROM and write to the
appropriate registers. Before the bridge registers can be accessed through the host, the autoload
condition should be verified by reading bit[3] offset 54h (EEPROM Autoload Status). The host
access is allowed only after the status of this bit becomes '1' which signifies that the autoload
initialization sequence has completed successfully.
EEPROM DATA STRUCTURE
The bridge will access the EEPROM one WORD at a time. The bit order during the address phase
is reverse that of the data phase. The data order starts with the MSB to the LSB during the address
phase, but starts with the LSB to the MSB during the data phase.
EEPROM CONTENT
EEPROM BYTE
ADDRESS
0A – 0Bh
0E – 0Fh
19 – 1Ch
1D – 20h
00 – 01h
04 – 05h
06 – 07h
10 – 11h
15 – 16h
17 – 18h
0Ch
0Dh
02h
03h
08h
09h
12h
13h
14h
CONFIGURATION
OFFSET
0A – 0Bh
5A – 5Bh
5C – 5Fh
00 – 01h
02 – 03h
42 – 43h
58 – 59h
60 – 63h
4Ah
09h
0Eh
0Fh
48h
4Fh
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REGION ENABLE
Vendor ID
Device ID
Reserved
Class Code – low byte of Class Code register
Header Type
Reserved
Arbiter Control Register
Memory Read Flow/Underflow Control
Upstream Memory Base and Limit Enable
Upstream Memory Base Register
Upstream Memory Limit Register
Upstream Memory Limit Upper 32-bit Register
DESCRIPTION
EEPROM SIGNATURE
Autoload will only proceed if it reads a value of 1516h on
the first word loaded.
Enables or disables certain regions of the PCI configuration
space from being loaded with contents in the EEPROM.
bit[0]: reserved
bit[4:1]: 0000 = stop autoload at offset 03h
bit[7:5]: reserved
ENABLE MISCELLANEOUS FUNCTIONS
bit[0]: ISA enable control bit write protect – When this it is
set, bridge will change bit[2] offset 3Eh into Read Only, and
the ISA enable feature will not be available.
Class Code – upper bytes of Class Code register
BIST
Arbiter Pre-emption Control (only bit[31:28])
Upstream Memory Base Upper 32-bit Register
0001 = stop autoload at offset 0Fh
0011 = stop autoload at offset 2Bh
other combinations are undefined
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A