PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 38

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.11.1
2.11.2
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made, indicating that no more data transfers will be made during this transaction.
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
MASTER TERMINATION INITIATED BY PI7C8154A
PI7C8154A, as an initiator, uses normal termination if DEVSEL# is returned by target within five
clock cycles of PI7C8154A’s assertion of FRAME# on the target bus. As an initiator, PI7C8154A
terminates a transaction when the following conditions are met:
If PI7C8154A is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The
address of the transaction is updated to reflect the address of the current DWORD to be delivered.
If PI7C8154A is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
MASTER ABORT RECEIVED BY PI7C8154A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by
the target within five clock cycles of the assertion of FRAME#, PI7C8154A terminates the
transaction with a master abort. This sets the received-master-abort bit in the status register
corresponding to the target bus.
For delayed read and write transactions, PI7C8154A is able to reflect the master abort condition
back to the initiator. When PI7C8154A detects a master abort in response to a delayed transaction,
and when the initiator repeats the transaction, PI7C8154A does not respond to the transaction with
DEVSEL#, which induces the master abort condition back to the initiator. The transaction is then
removed from the delayed transaction queue. When a master abort is received in response to a
posted write transaction, PI7C8154A discards the posted write data and makes no more attempts to
deliver the data. PI7C8154A sets the received-master-abort bit in the status register when the
master abort is received on the primary bus, or it sets the received master abort bit in the secondary
Target disconnect with data transfer
Target disconnect without data transfer
Target abort
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers
to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the
master latency timer expires and the PI7C8154A’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
Page 38 of 112
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A