PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 18

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.6
MISCELLANEOUS SIGNALS
Name
S_CLKIN
S_CLKOUT[9:0]
Name
MSK_IN
P_VIO
S_VIO
BPCCE
CONFIG66
PMEENA#
Pin #
J4
P1, P2, P3, N1, N3, M2,
M1, M3, L3, L2
Pin #
R21
R20
N22
R4
R22
D11
Page 18 of 112
Type
Type
O
I
I
I
I
I
I
I
Description
Secondary Clock Input: Provides timing for all
transactions on the secondary interface.
Secondary Clock Output: Provides secondary
clocks phase synchronous with the P_CLK.
When these clocks are used, one of the clock
outputs must be fed back to S_CLKIN. Unused
outputs may be disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins
and MSK_IN
3. Terminating them electrically.
Description
Secondary Clock Disable Serial Input: This pin is
used by bridge to disable secondary clock outputs.
The serial stream is received by MSK_IN, starting
when P_RESET is detected deasserted and
S_RESET# is detected as being asserted. The serial
data is used for selectively disabling secondary
clock outputs and is shifted into the secondary clock
control configuration register. This pin can be tied
LOW to enable all secondary clock outputs or tied
HIGH to drive all the secondary clock outputs
HIGH.
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus.
P_VIO must be tied to 3.3V only when all devices
on the primary bus use 3.3V signaling. Otherwise,
P_VIO is tied to 5V.
Secondary I/O Voltage: This pin is used to
determine either 3.3V or 5V signaling on the
secondary bus. S_VIO must be tied to 3.3V only
when all devices on the secondary bus use 3.3V
signaling. Otherwise, S_VIO is tied to 5V.
Bus/Power Clock Control Management Pin:
When this pin is tied HIGH and the bridge is placed
in the D2 or D3
to place the secondary bus in the B2 power state.
The secondary clocks are disabled and driven to 0.
When this pin is tied LOW, there is no effect on the
secondary bus clocks when the bridge enters the D2
or D3
66MHz Configuration: This pin indicates if the
bridge is capable of running at 66MHz operation.
Tie HIGH to set bit [21] of offset 04h of the status
register.
Power Management Enable Support: This pin
sets bits [31:27] offset DEh of the Power
Management Capabilities Register.
LOW, bits [31:27] offset DEh are set to 11111 to
indicate that the secondary devices are capable of
asserting PME#. When this pin is tied HIGH, bits
[31:27] offset DEh are set to 00000 to indicate
that PI7C8154A does not support the PME# pin.
For Intel 21154, this pin is defined as VDD. For
more info, please refer to Appendix on page 113.
HOT
power state.
HOT
power state, it enables the bridge
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
When tied
PI7C8154A