PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 61

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4
Note: x=don’t care
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
Table 5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
Note: x=don’t care
SYSTEM ERROR (SERR#) REPORTING
PI7C8154A uses the P_SERR# signal to report conditionally a number of system error conditions
in addition to the special case parity error conditions described in Section 5.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following
conditions apply:
In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR#
when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit
is set in the bridge control register. In addition, the bridge also sets the received system error bit in
the secondary status register.
The bridge also conditionally asserts P_SERR# for any of the following reasons:
1
0
0
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
2
2
3
(asserted)
PI7C8154A has detected P_PERR# asserted on an upstream posted write transaction or
S_PERR# asserted on a downstream posted write transaction.
PI7C8154A did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit on the
bridge control register must both be set.
The SERR# enable bit must be set in the command register.
For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the
command register.
Whenever the bridge asserts P_SERR#, PI7C8154A must also set the signaled system error bit
in the status register.
S_PERR#
P_SERR#
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Transaction Type
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Direction
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
x / x
1 / 1
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / 1
x / x
Primary/ Secondary Parity
Primary / Secondary Parity
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A