PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 64

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.2
6.3
7
LOCKED TRANSACTION IN UPSTREAM DIRECTION
The bridge ignores upstream lock and transactions. The bridge will pass these transactions as
normal transactions without lock established.
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, the bridge must maintain the
lock on the target bus for any subsequent locked transactions until the initiator relinquishes the
lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked
sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of
the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. The bridge does
not know whether the current transaction is the last one in a sequence of locked transactions until
the initiator de-asserts the LOCK# signal at end of the transaction.
When the last locked transaction is a delayed transaction, the bridge has already completed the
transaction on the target bus. In this example, as soon as the bridge detects that the initiator has
relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-
asserted, the bridge de-asserts the LOCK# signal on the target bus as soon as possible. Because of
this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction
has been completed on the target bus. As soon as the bridge has de-asserted LOCK# to indicate the
end of a sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, the bridge de-asserts LOCK# on the
target bus at the end of the transaction because the lock was relinquished at the end of the write
transaction on the initiator bus.
When the bridge receives a target abort or a master abort in response to a locked delayed
transaction, the bridge returns a target abort or a master abort when the initiator repeats the locked
transaction. The initiator must then de-assert LOCK# at the end of the transaction. The bridge sets
the appropriate status bits, flagging the abnormal target termination condition (see Section 2.11).
Normal forwarding of unlocked posted and delayed transactions is resumed.
When PI7C8154A receives a target abort or a master abort in response to a locked posted write
transaction, PI7C8154A cannot pass back that status to the initiator. PI7C8154A asserts SERR# on
the initiator bus when a target abort or a master abort is received during a locked posted write
transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for
the master abort condition if the master abort mode bit is set in the bridge control register (see
Section 5.4).
PCI BUS ARBITRATION
The bridge must arbitrate for use of the primary bus when forwarding upstream transactions. Also,
it must arbitrate for use of the secondary bus when forwarding downstream transactions. The
arbiter for the primary bus resides external to the bridge, typically on the motherboard. For the
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ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A