ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 94

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 9-2:
DS39935C-page 92
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9
bit 8
bit 7
bit 6-5
bit 4
bit 3-0
Note 1:
DEFER
U-0
R-0
—
(1)
Applicable in Half-Duplex mode only; collisions and deferrals are not possible in Full-Duplex mode.
Unimplemented: Read as ‘ 0 ’
Reserved: Ignore on read
LATECOL: Transmit Late Collision Status bit
1 = A collision occurred after transmitting more than MACLCONH + 8 bytes. The last transmission was
0 = No late collision occurred during the last transmission
MAXCOL: Transmit Maximum Collisions Status bit
1 = MACLCONL + 1 collisions occurred while transmitting the last packet. The last transmission was
0 = MACLCONL or less collisions occurred while transmitting the last packet
EXDEFER: Transmit Excessive Defer Status bit
1 = The medium was busy with traffic from other nodes for more than 24,288 bit times. The last
0 = The MAC deferred for less than 24,288 bit times while transmitting the last packet
DEFER: Transmit Defer Status bit
1 = The medium was busy with traffic from other nodes, so the MAC was forced to temporarily defer
0 = No transmit deferral or an excessive deferral occurred while attempting to transmit the last packet
Reserved: Ignore on read
CRCBAD: Transmit CRC Incorrect Status bit
1 = The FCS field of the last packet transmitted did not match the CRC internally generated by the
0 = The FCS field of the last packet transmitted was correct or the MAC is configured to append an
COLCNT<3:0>: Transmit Collision Count Status bits
Number of collisions that occurred while transmitting the last packet.
aborted.
aborted.
transmission was aborted.
transmission of the last packet
MAC during transmission
internally generated CRC
U-0
R-0
—
r
ETXSTAT: ETHERNET TRANSMIT STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
R-0
—
r
CRCBAD
(1)
R-0
R-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLCNT3
(1)
(1)
R-0
R-0
r
(1)
(1)
(1)
COLCNT2
LATECOL
R-0
R-0
(1)
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
COLCNT1
MAXCOL
R-0
R-0
(1)
(1)
EXDEFER
COLCNT0
R-0
R-0
bit 8
bit 0
(1)
(1)