ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 53

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

 2010 Microchip Technology Inc.
5.0
ENC424J600/624J600
interface directly with the parallel port available on
many microcontrollers, including the Parallel Master
Port (PMP) available on many Microchip PIC
controllers. The Parallel Slave Port interface is highly
flexible, and can communicate using either Intel
Motorola
the event that a parallel port is not available on the host
microcontroller, a software-managed parallel interface
derived from general purpose I/O pins can be used.
When the PSP interface is enabled, the ENCX24J600
functions as a slave device on the parallel bus. The
host controller must be configured to generate the
destination or target address on the slave device, as
well as the necessary port control signals.
5.1
The PSP interface is mutually exclusive with the serial
interface. To enable the PSP and disable the SPI, tie
the INT/SPISEL pin to Vss through an external resistor.
The PSP interface can use from 12 to 34 pins, depend-
ing on the device pin count and the PSP operating
mode. There are up to eight modes, covering the
permutations of data widths, data/address multiplexing
and bus strobe formats. The modes are selected by
TABLE 5-1:
Note 1:
Mode
PSP
10
1
2
3
4
5
6
9
®
PARALLEL SLAVE PORT
INTERFACE (PSP)
Physical Implementation
formats for read and write control strobes. In
Includes only address, data and port control strobes. INT/SPISEL and PSPCFG pins used for mode
configuration are not included.
44-pin 64-pin
Availability
X
X
OPERATING MODES SUPPORTED BY THE PSP INTERFACE
X
X
X
X
X
X
X
X
devices
Min
19
19
26
26
12
12
19
19
# Pins
are
Max
(1)
26
26
34
34
19
19
21
21
designed
®
micro-
Width
16 bit
16 bit
16 bit
16 bit
Data
8 bit
8 bit
8 bit
8 bit
®
or
to
Address/Data
Multiplexing
ENC424J600/624J600
Yes
Yes
Yes
Yes
No
No
No
No
tieing each of the PSPCFG<4:0> pins to either V
V
performance metrics are summarized in Table 5-1.
Additional information on physical connections are
provided in Section 2.7.2 “PSP”.
In PSP mode, the CS/CS pin becomes the active-high
Chip Select (CS) pin. A weak internal pull-down is auto-
matically connected to the pin when the PSP interface
is selected, preventing the pin from floating to an
indeterminate state when an external Chip Select
signal is absent.
When CS is in the inactive (logic-low) state, the AD15
(64-pin devices only) and AD<14:0> pins are placed in
a high-impedance state and are 5V tolerant. This
allows the ENCX24J600 to share a single parallel bus
with other slave devices that function the same way
while deselected. All other PSP pins, including the
A<14:0> pins (64-pin devices only) and the port control
strobes, are 5V tolerant inputs at all times. Inputs on
these pins are ignored while the chip select pin is at
logic low.
Unlike the SPI port, the use of chip select is optional
with the PSP. The CS pin can be tied permanently to
V
devices. This saves one I/O pin from the host controller
while leaving the ENCX24J600 in a perpetually
selected state.
SS
DD
. The available combinations along with relative
if the parallel bus is not shared with other slave
CS, R/W, B0SEL, B1SEL
AL, CS, RD, WRL, WRH
AL, CS, R/W, B0SEL,
CS, RD, WRL, WRH
AL, CS, EN, R/W
AL, CS, RD, WR
Control Lines
CS, EN, R/W
CS, RD, WR
B1SEL
DS39935C-page 51
Performance
Theoretical
@ 10 MHz
(Mbit/s)
<80
<80
<80
160
160
<80
80
80
DD
or