ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 125

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
ENC424J600/624J600 devices incorporate a Direct
Memory Access (DMA) controller to reduce the burden
on the host processor. The module serves the following
purposes:
• Copying data from one part of the packet buffer to
• Copying data between the packet buffer and one
• Calculating a 16-bit checksum over a block of
In general, the application configures the DMA opera-
tion parameters (such as source and destination
addresses), then sets the DMAST (ECON1<5>) bit to
start the transfer or calculation. The hardware auto-
matically clears the bit when the operation finishes.
Additionally, the module can be configured to set an
interrupt
Section 13.0 “Interrupts” .
The
wrap-around logic as the indirect memory access
interfaces described in Section 3.5.5 “Indirect SRAM
Buffer Access” . When a read or write operation
reaches the end of the User-Defined Area (UDA)
specified by
EUDAST. When an operation reaches the end of the
general purpose buffer, as indicated by ERXST – 1, it
automatically wraps to 0000h. Finally, when an opera-
tion reaches the end of the receive buffer (the last
address in the physical memory space), it automatically
wraps to ERXST. If any of these areas share an ending
address, the UDA wrapping will take priority, followed
by the general purpose buffer wrapping, then the
receive buffer. The wrap-around applies to both the
source and destination addresses as an operation
progresses.
Although memory is organized by the 16-bit word, the
DMA accepts any byte address as the source and
destination. It is also capable of operation over an even
or an odd number of bytes. Internally, the DMA uses
16-bit accesses, so optimal efficiency is achieved when
both the source and destination addresses are even, or
when both are odd. Copy operations from an odd
source address to an even destination address or vice
versa are allowed; however, performance will be dimin-
ished by approximately 50% relative to copy operation
on addresses that are aligned to each other.
 2010 Microchip Technology Inc.
another.
of the memory mapped cryptographic engines.
data, compatible with the checksum used in
standard protocols, such as IP and TCP.
DMA
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
flag
module
EUDAND, it automatically wraps to
on
completion,
follows the
as
same
detailed
address
in
ENC424J600/624J600
It is recommended that DMA configuration parameters
(such as address pointers and operation selection bits)
not be modified while DMAST (ECON1<5>) is set and
the DMA is active. This requirement is additionally true
for the EUDAND Pointer, even if it is not located any-
where within the source or destination memory ranges
of the DMA. After processing each memory word, the
DMA performs the necessary address wrap-around
checks to increment to the next address(es). If the host
controller writes to EUDAND at the exact moment the
DMA is performing an address wrap-around check, it is
possible that the EUDAND register will be in a
temporary incoherent state and the DMA source or
destination address will wrap to the EUDAST value
unintentionally.
Depending upon the operation and the alignment of the
source and destination addresses, the DMA module
typically requires between one and three clock cycles
of OSC1 per 16-bit word. Any DMA operation in
progress can be cancelled by clearing the DMAST bit.
14.1
The DMA can copy any length of data from any address
to any destination, including the corner case when the
length is zero. Source and destination addresses may
be within the implemented SRAM area (0000h through
5FFFh) or the cryptographic data area (7800h through
7C4Fh). It is not possible to use the DMA to read or
write from SFRs.
Before initiating the first copy operation, verify that the
ETHEN (ECON2<15>) and CLKRDY (ESTAT<12>)
bits are set. This does not need to be done for
subsequent operations.
To copy data from one location to another:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Verify that the values of ERXST, EUDAND and
EUDAST (if applicable) are selecting the
desired buffer wrapping configuration.
Verify that DMAST (ECON1<5>) is clear,
indicating that the module is Idle.
Set DMACPY (ECON1<4>) to select a copy
operation.
Optionally, set DMANOCS (ECON1<2>) to
prevent a checksum calculation.
Set EDMAST to point to the source address.
Set EDMADST to point to the destination
address.
Set EDMALEN to indicate the number of bytes
to copy.
Set DMAST to initiate the operation.
Wait for the hardware to clear DMAST to indicate
completion. If the DMA interrupt is enabled, it will
be triggered when DMAST is cleared.
Copying Memory
DS39935C-page 123