ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 82

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 8-3:
DS39935C-page 80
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9-8
bit 7-5
bit 4
bit 3
PADCFG2
R/W-1
U-0
—
Unimplemented: Read as ‘ 0 ’
DEFER: Defer Transmission Enable bit (applies to half duplex only)
1 = When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting
0 = When the medium is occupied, the MAC will abort the transmission after the excessive deferral
BPEN: No Backoff During Back Pressure Enable bit (applies to half duplex only)
1 = After incidentally causing a collision during back pressure, the MAC immediately begins retransmitting
0 = After incidentally causing a collision during backpressure, the MAC delays using the binary
NOBKOFF: No Backoff Enable bit (applies to half duplex only)
1 = After any collision, the MAC immediately begins retransmitting
0 = After any collision, the MAC delays using the binary exponential backoff algorithm before
Unimplemented: Read as ‘ 0 ’
Reserved: Write as ‘ 0 ’
PADCFG<2:0>: Automatic Pad and CRC Configuration bits
111 = All short frames are zero-padded to 64 bytes and a valid CRC is then appended
110 = No automatic padding of short frames
101 = MAC automatically detects VLAN protocol frames which have a 8100h type field and auto-
100 = No automatic padding of short frames
011 = All short frames are zero-padded to 64 bytes and a valid CRC is then appended
010 = No automatic padding of short frames
001 = All short frames will be zero-padded to 60 bytes and a valid CRC is then appended
000 = No automatic padding of short frames
TXCRCEN: Transmit CRC Enable bit
1 = MAC appends a valid CRC to all frames transmitted regardless of the PADCFG bits. TXCRCEN
0 = MAC does not append a CRC. The last 4 bytes are checked and if it is an invalid CRC, it is to be
PHDREN: Proprietary Header Enable bit
1 = Frames presented to the MAC contain a 4-byte proprietary header which is not used when
0 = No proprietary header is present; the CRC covers all data (normal operation)
PADCFG1
DEFER
R/W-1
R/W-0
to transmit (use this setting for IEEE 802.3 compliance)
limit is reached (24,288 bit times)
exponential backoff algorithm before attempting to retransmit (normal operation)
attempting to retransmit (normal operation)
must be set if the PADCFG bits specify that a valid CRC will be appended.
reported by setting CRCBAD (ETXSTAT<4>).
calculating the CRC
matically pad to 64 bytes. If the frame is not a VLAN frame, it will be padded to 60 bytes. After
padding, a valid CRC is appended.
MACON2: MAC CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
PADCFG0
R/W-0
R/W-1
BPEN
NOBKOFF
TXCRCEN
R/W-0
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PHDREN
R/W-0
U-0
—
HFRMEN
R/W-0
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-1
r
r
FULDPX
R/W-0
R/W-0
r
bit 8
bit 0