ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 84

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 8-5:
REGISTER 8-6:
DS39935C-page 82
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-8
bit 7
bit 6-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7-4
bit 3-0
U-0
U-0
U-0
U-0
—
—
—
—
Unimplemented: Read as ‘ 0 ’
Reserved: Write as ‘ 0001100 ’ (0Ch)
Unimplemented: Read as ‘ 0 ’
IPG<6:0>: Non Back-to-Back Inter-Packet Gap Delay Time Control bits
Inter-Packet Gap (IPG) between the end of one packet received or transmitted and the start of the next
packet transmitted. For maximum performance while meeting IEEE 802.3 compliance, leave this field
set to 12h, which represents an Inter-Packet Gap time of 0.96  s (at 100 Mb/s) or 9.6  s (at 10 Mb/s).
Unimplemented: Read as ‘ 0 ’
Reserved: Write as ‘ 110111 ’ (37h)
Unimplemented: Read as ‘ 0 ’
MAXRET<3:0>: Maximum Retransmissions Control bits (half duplex only)
Maximum retransmission attempts the MAC will make before aborting a packet due to excessive
collisions.
R/W-0
R/W-0
IPG6
U-0
U-0
—
—
r
MAIPG: MAC INTER-PACKET GAP REGISTER
MACLCON: MAC COLISION CONTROL REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-0
R/W-0
R/W-1
IPG5
U-0
—
r
r
R/W-0
R/W-1
R/W-1
IPG4
U-0
—
r
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MAXRET3
R/W-1
R/W-0
R/W-0
R/W-1
IPG3
r
r
MAXRET2
R/W-1
R/W-0
R/W-1
R/W-1
IPG2
r
r
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
MAXRET1
R/W-0
R/W-1
R/W-1
R/W-1
IPG1
r
r
MAXRET0
R/W-0
R/W-0
R/W-1
R/W-1
IPG0
r
r
bit 8
bit 0
bit 8
bit 0