ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 57

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.2
PSP Mode 2 is also an 8-bit, fully demultiplexed mode
that is available on 64-pin devices only. The parallel
interface consists of 8 bidirectional data pins (AD<7:0>)
and 9 to 15 separate address pins (A<14:0>). To select
PSP Mode 2, tie PSPCFG2 and PSPCFG3 to V
while connecting PSPCFG4 to V
demonstrates connections required to use Mode 2.
This mode uses a combined Read/Write (R/W) select,
an Enable (EN) strobe pin and a separate Chip Select
pin (CS). These three pins allow the host to select the
device, indicate whether a read or write operation is
desired and signal when valid data is being presented
A logic high signal on the R/W pin indicates that a read
operation is to be performed when the EN strobe is
asserted, while a logic low indicates that a write opera-
tion is to be performed. The state of R/W only affects
the data bus state when the EN signal is active. When
either CS, EN or R/W is driven low, the data bus stays
in a high-impedance state.
FIGURE 5-4:
 2010 Microchip Technology Inc.
Note 1: Use of the CS strobe from the controller is optional. If not used, tie CS to V
2: Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V
3: Use of the external interrupt signal to the controller is optional.
MODE 2
addressing is desired.
DEVICE CONNECTIONS FOR PSP MODE 2
Host MCU
PMRD/PMWR
PMA<14:9>
PMD<7:0>
PMA<8:0>
PMENB
DD
PMCSx
INTx
. Figure 5-4
(3)
SS
+3.3V
,
9
6
8
ENC424J600/624J600
To perform a read operation:
1.
2.
3.
4.
5.
When EN is raised high, the data bus begins to drive
out indeterminate data for a brief period, then switches
to the correct read data after the appropriate read
access time has elapsed. When the EN strobe is low-
ered, the data bus pins return to a high-impedance
state.
To perform a write operation:
1.
2.
3.
4.
5.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-5 and Figure 5-6,
respectively.
100 k 
Raise the CS line (if connected to the host).
Raise the R/W signal.
Present the address to be read onto the address
bus.
Raise the EN strobe.
Wait the required time for the access to occur.
Raise the CS line (if connected to the host).
Lower the R/W signal.
Present the address onto the address bus.
Present the data on the data bus.
Strobe the EN signal high and then low.
CS
R/W
EN
A<14:9>
A<8:0>
AD<7:0>
INT/SPISEL
PSPCFG2
PSPCFG3
PSPCFG4
(1)
ENC624J600
(2)
DD
.
DD
when only indirect
DS39935C-page 55