ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 116

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 12-6:
DS39935C-page 114
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-0
LP100
LPNP
R-0
R-0
LPNP: Link Partner Next Page Ability bit
1 = Link partner PHY supports auto-negotiation next page abilities
0 = Link partner PHY does not support auto-negotiation next page abilities
LPACK: Link Partner Acknowledge Local PHY Code Word Status bit
1 = Link partner PHY has successfully received the local PHY abilities saved in PHANA
0 = Link partner PHY has not received the local PHY abilities saved in PHANA
LPFAULT: Link Partner Remote Fault Condition bit
1 = Link partner PHY has a Fault condition present
0 = Link partner PHY does not have a Fault condition present
Reserved: Ignore on read
LPPAUS<1:0>: Link Partner PAUSE Flow Control Ability bits
11 = Link partner supports both symmetric PAUSE and asymmetric PAUSE toward local device. Link
10 = Link partner supports asymmetric PAUSE toward local device only; it can transmit PAUSE control
01 = Link partner supports symmetric PAUSE only, and generates and responds to PAUSE control
00 = Link partner does not support PAUSE flow control
LP100T4: Link Partner 100Base-T4 Ability bit
1 = Link partner PHY is capable of operating in 100Base-T4 mode
0 = Link partner PHY is incapable of operating in 100Base-T4 mode
LP100FD: Link Partner 100Base-TX Full-Duplex Ability bit
1 = Link partner PHY is capable of 100Base-TX full-duplex operation
0 = Link partner PHY is incapable of 100Base-TX full-duplex operation
LP100: Link Partner 100Base-TX Half-Duplex Ability bit
1 = Link partner PHY is capable of 100Base-TX half-duplex operation
0 = Link partner PHY is incapable of 100Base-TX half-duplex operation
LP10FD: Link Partner 10Base-T Full-Duplex Ability bit
1 = Link partner PHY is capable of 10Base-T full-duplex operation
0 = Link partner PHY is incapable of 10Base-T full-duplex operation
LP10: Link Partner 10Base-T Half-Duplex Ability bit
1 = Link partner PHY is capable of 10Base-T half-duplex operation
0 = Link partner PHY is incapable of 10Base-T half-duplex operation
LPIEEE<4:0>: Link Partner IEEE Standard Selector Field bits
00001 = IEEE 802.3 Std.
All other values are reserved by IEEE. Remote node should also specify this as the selector value.
LP10FD
LPACK
R-0
R-0
partner generates and responds to PAUSE control frames. Alternatively, if the local device only
supports asymmetric PAUSE, the link partner will respond to PAUSE control frames, but not
generate any.
frames, but cannot act upon PAUSE frames sent to it
frames
PHANLPA: PHY AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER
W = Writable bit
‘1’ = Bit is set
LPFAULT
LP10
R-0
R-0
LPIEEE4
R-0
R-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
LPPAUS1
LPIEEE3
R-0
R-0
LPPAUS0
LPIEEE2
R-0
R-0
 2010 Microchip Technology Inc.
x = Bit is unknown
LP100T4
LPIEEE1
R-0
R-0
LP100FD
LPIEEE0
R-0
R-0
bit 8
bit 0