ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 17

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.7.3
The chip select functions for the serial and parallel
interfaces are shared on one common pin, CS/CS. This
pin is equipped with both internal weak pull-up and
weak pull-down resistors. If the SPI interface is
selected (CS), the pull-up resistor is automatically
enabled and the pull-down resistor is disabled. If the
PSP interface is chosen (CS), the pull-down resistor is
automatically enabled and the pull-up resistor is
disabled. This allows the CS/CS pin to stay in the
unselected state when not being driven, avoiding the
need for an external board level resistor on this pin.
When enabled by using SPI mode, the internal weak
pull-up only pulls the CS/CS pin up to approximately
V
any loading; it does not pull all the way to V
using the PSP interface, the pull-down will be enabled,
which is capable of pulling all the way to V
unloaded.
2.8
All digital output pins on ENC424J600/624J600
devices contain CMOS output drivers that are capable
of sinking and sourcing up to 18 mA continuously. All
digital inputs and I/O pins operating as inputs are 5V
tolerant. These features generally mean that the
ENCX24J600 can connect directly to the host
microcontroller without the need of any glue logic.
However, some consideration may be necessary when
interfacing with 5V systems.
Since the digital outputs drive only up to the V
voltage (3.3V nominally), the voltage may not be high
enough to ensure a logical high is detected by 5V
systems which have high input thresholds. In such
cases, unidirectional level translation from the 3.3V
ENCX24J600 up to the 5V host microcontroller may be
needed.
When using the SPI interface, an economical 74HCT08
(quad AND gate), 74ACT125 (quad 3-state buffer) or
other 5V CMOS chip with TTL level input buffers may
be used to provide the necessary level shifting. The
use of 3-state buffers permits easy integration into
systems which share the SPI bus with other devices.
However, users must make certain that the propaga-
tion delay of the level translator does not reduce the
maximum SPI frequency below desired levels.
Figure 2-10 and Figure 2-11 show two example
translation schemes.
When using the PSP interface, eight, or all sixteen of
the ADx pins, may need level translation when perform-
ing read operations on the ENCX24J600. The 8-bit
74ACT245 or 16-bit 74ACT16245 bus transceiver, or
similar devices, may be useful in these situations.
 2010 Microchip Technology Inc.
DD
-1.1V or around 2.2V at typical conditions without
Digital I/O Levels
CS/CS PIN
DD
SS
. When
when
DD
ENC424J600/624J600
FIGURE 2-10:
FIGURE 2-11:
MCU
MCU
OSC1
OSC1
SDO
INTx
SCK
INTx
SDO
SCK
SDI
SDI
I/O
I/O
100k
LEVEL SHIFTING ON THE
SPI INTERFACE USING
AND GATES
LEVEL SHIFTING ON THE
SPI INTERFACE USING
3-STATE BUFFERS
100k
3.3V
3.3V
DS39935C-page 15
CLKOUT
INT/SPISEL
SO
SCK
SI
CS
INT/SPISEL
CLKOUT
SO
SCK
SI
CS
ENCX24J600
ENCX24J600