ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 92

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 9-1:
DS39935C-page 90
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7-6
MODEXST
FCOP1
R/W-0
R/W-0
MODEXST: Modular Exponentiation Start bit
1 = Modular exponentiation calculation started/busy; automatically cleared by hardware when done
0 = Modular exponentiation calculation done/Idle
HASHEN: MD5/SHA-1 Hash Enable bit
1 = MD5/SHA-1 hashing engine enabled. Data written to the hashing engine by the DMA is added to
0 = MD5/SHA-1 hashing engine disabled
HASHOP: MD5/SHA-1 Hash Operation Control bit
1 = MD5/SHA-1 hash engine loads the Initial Value (IV) from the hash memory. This mode is typically
0 = Normal MD5/SHA-1 hash operation
HASHLST: MD5/SHA-1 Hash Last Block Control bit
1 = The next DMA transfer to the hash engine completes the hash. If needed, padding is automatically
0 = The next DMA transfer to the hash engine adds data to the hash. Further data additions to the hash
AESST: AES Encrypt/Decrypt Start bit
1 = AES encrypt/decrypt operation is started/busy; automatically cleared by hardware when done
0 = AES encrypt/decrypt operation is done/Idle
AESOP<1:0>: AES Operation Control bits
11 = Reserved
10 = ECB/CBC decrypt
01 = CBC/CFB encrypt
00 = ECB/CFB/OFB encrypt or key initialization
PKTDEC: RX Packet Counter Decrement Control bit
1 = Decrement PKTCNT (ESTAT<7:0>) bits by one. Hardware immediately clears PKTDEC to ‘ 0 ’,
0 = Leave PKTCNT bits unchanged
FCOP<1:0>: Flow Control Operation Control/Status bits
When FULDPX (MACON2<0>) = 1 :
11 = End flow control by sending a pause frame with 0000h pause timer value; automatically cleared
10 = Enable flow control by periodically sending pause frames with a pause timer defined by EPAUS
01 = Transmit single pause frame defined by EPAUS; automatically cleared by hardware when done
00 = Flow control disabled/Idle
When FULDPX (MACON2<0>) = 0 :
1x , 01 = Enable flow control by continuously asserting backpressure (transmitting preamble)
00
HASHEN
FCOP0
R/W-0
R/W-0
the hash.
used for HMAC hash operations.
generated and added to the hash.
are still possible.
allowing back-to-back decrement operations.
by hardware when done
ECON1: ETHERNET CONTROL REGISTER 1
= Flow control disabled/Idle
W = Writable bit
‘1’ = Bit is set
HASHOP
DMAST
R/W-0
R/W-0
HASHLST
DMACPY
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DMACSSD
AESST
R/W-0
R/W-0
DMANOCS
AESOP1
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
AESOP0
TXRTS
R/W-0
R/W-0
PKTDEC
R/W-0
R/W-0
RXEN
bit 8
bit 0