ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 89

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

It is possible for the host application to write to the
receive buffer. However, it is recommended not to do
so outside of the area protected by the Tail Pointer in
order to prevent it from being subsequently overwritten
by future receive packets.
ERXHEAD is a read-only register and may be updated
at any time by hardware. The high byte is shadowed to
ensure it can be safely read on 8-bit interfaces (SPI or
PSP). When reading ERXHEAD, read the low byte first.
This operation simultaneously copies the high byte to a
shadow register. Reading the high byte automatically
reads from this shadow register. This ensures that the
value has not been modified since the low byte was
obtained, even if another packet has been received in
the interim.
9.2.1
Once the MAC and PHY are properly initialized, the
device is ready to begin receiving packets.
To enable reception:
1.
2.
3.
4.
5.
Once RXEN is set, it is recommended that ERXST not
be modified. The host controller must monitor the
ENCX24J600 to determine when a packet has arrived
and is ready to be processed. This is accomplished by
using the packet pending interrupt as described in
Section 13.1.5
Alternatively, poll the PKTCNT bits for a non-zero
value.
 2010 Microchip Technology Inc.
Program the ERXST Pointer (low byte first if
writing a byte at a time) to the first address to be
used for the receive buffer. This pointer must
indicate an even address. The Head Pointer,
ERXHEAD, will automatically be set to the same
value.
In the host controller application, create a
variable, NextPacketPointer , to hold the
address value of the next received packet.
Initialize this variable to be equal to the current
value of ERXST.
Program the Tail Pointer, ERXTAIL, to the last
even address of the buffer or 5FFEh.
Configure
Section 13.0 “Interrupts” for more information.
Set RXEN (ECON1<0>) to enable reception.
CONFIGURING PACKET
RECEPTION
interrupts
“Received
as
Packet
desired.
Pending” .
See
ENC424J600/624J600
9.2.2
Packets are stored sequentially in the receive buffer.
Each frame is stored as it was presented to the MAC,
including all padding and frame check (CRC) bytes, but
excluding any preamble or start of stream/frame delim-
iter bytes. Frames are always saved starting on an
even address, so those with an odd length skip one
byte before the next frame begins. A sample packet
stored in memory is shown in Figure 9-4.
When a packet is received, the hardware increments
the Packet Counter bits, PKTCNT (ESTAT<7:0>).
Incoming bytes are written sequentially, beginning at
the Head Pointer, ERXHEAD. If the Head Pointer
reaches the Tail Pointer, ERXTAIL, during reception, or
if incrementing the PKTCNT bits would cause an over-
flow, the packet will be discarded and the Head Pointer
restored.
Each received frame is preceded in memory by a
pointer to the next frame and a Receive Status Vector
(RSV). The RSV includes the length of the frame, and
flags indicating the type of packet and which filters
were matched. This format of the RSV is shown in
Table 9-1.
To retrieve a packet from the buffer:
1.
2.
3.
4.
5.
6.
7.
Verify that a packet is waiting by ensuring that
the PKTCNT<7:0> bits are non-zero or that
PKTIF (EIR<6>) is set.
Begin reading at address pointed to by the
application
(see
Reception” ).
Read the first two bytes of the packet, which are
the address of the next packet and write to
NextPacketPointer .
Read the next six bytes, which are the Receive
Status Vector (RSV).
Read the Ethernet frame. The number of bytes
to be read is indicated by the received byte
count in the RSV read during step 4.
As the frame is read and processed, incremental
amounts of memory buffer can be freed up by
updating the ERXTAIL Pointer value to the point
where the packet has been processed, taking
care to wrap back at the end of the received
memory buffer. Once the whole frame has been
processed, the final value of ERXTAIL should be
equal to ( NextPacketPointer – 2).
Set PKTDEC (ECON1<8>) to decrement the
PKTCNT bits. PKTDEC is automatically cleared
by hardware if PKTCNT decrements to zero.
Section 9.2.1
STORAGE OF INCOMING PACKETS
variable,
“Configuring
NextPacketPointer
DS39935C-page 87
Packet