ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 35

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5.1
The general purpose buffer memory starts at address
0000h and includes all memory up to, but not including,
the memory address pointed to by the ERXST register
(i.e., ERXST – 1).
This buffer can be used to store transmit packets,
received data that the host controller wishes to save for
an extended period, or any type of volatile or state
information that the host controller does not have room
internally to save. Upper layer communications proto-
cols and applications, such as a TCP/IP stack with SSL
or TLS security, are generally infeasible or will perform
poorly over high latency Internet links without using
large buffers.
For reliable, connection oriented protocols like TCP, the
maximum theoretical throughput is directly proportional
to the round trip Acknowledgement latency of the link
and the size of the corresponding transmit or receive
buffer. The general purpose buffer memory on the
ENCX24J600 is well suited for use by TCP for
implementing
across the Internet, where round trip Acknowledgement
latency is in the order of many milliseconds.
3.5.2
The receive buffer constitutes a circular FIFO buffer
managed by hardware. The buffer extends inclusively
from the byte pointed to by the ERXST Pointer, to the
very end of the SRAM at address 5FFFh. The size of
the buffer, in bytes, is therefore defined as:
As bytes of data are received from the Ethernet
interface, they are written into the receive buffer
sequentially. However, after the memory at address
5FFFh is written to, the hardware will automatically
wrap around and write the next byte of received data to
the ERXST address. As a result, the receive hardware
will never write outside the boundaries of the RX FIFO
buffer.
For proper 16-bit word alignment, the ERXST Pointer is
required to point to an even memory address. The
Least Significant bit of this register is read-only and
fixed as ‘0’ to force even alignment. All other
implemented bits in this register are read/write and can
be programmed by software to point to any even
address, from 0000h to 5FFEh.
The default value of ERXST on device Reset is 5340h.
This allocates 21,312 bytes to the general purpose
buffer and 3,264 bytes to the RX buffer. This RX buffer
size is adequate to store at least two maximum length
Ethernet frames, or any combination of numerous
smaller packets.
 2010 Microchip Technology Inc.
RX Buffer Size = 5FFFh – ERXST + 1
RECEIVE BUFFER
GENERAL PURPOSE BUFFER
high-performance
communications
ENC424J600/624J600
The host controller may only program the ERXST
Pointer when the receive logic is disabled. The pointer
must not be modified while the receive logic is enabled
by having RXEN (ECON1<0>) set.
The receive memory is always accessible to the RX
hardware, regardless of transmit, DMA operations or
host controller read/write operations, which may be
accessing
hardware will never drop a packet due to insufficient
memory access bandwidth.
3.5.3
The ENC624J600 family does not implement a dedi-
cated transmit buffer. The transmit hardware has the
flexibility of transmitting data starting at any memory
address, including odd memory addresses which are
off of a 16-bit word boundary. The host controller can
transmit data from either the general purpose area or
RX FIFO area of the entire 24 Kbytes of SRAM.
Because of the transmit flexibility, the host controller may
store many prebuilt packets in the general purpose
buffer for quick transmission. Alternatively, because the
hardware can transmit data from the receive buffer, it is
possible to quickly modify certain packet header fields
and retransmit received packets without reading the
entire packet contents into the host microcontroller. This
feature may improve performance on certain proxy,
gateway or echoing (“ping”) applications.
The transmit hardware performs reads from the SRAM
only; it never writes anything into the SRAM.
The entire SRAM is always accessible to the TX
hardware, regardless of the receive activity, DMA
operations or host controller read/write operations,
which may be simultaneously attempting to access the
SRAM.
3.5.4
When one of the PSP interfaces is used, the SRAM
buffer is directly accessible through the interface.
Assuming that all necessary address lines are con-
nected, all addresses in the memory maps shown in
Figure 3-2 (except for the cryptographic data memory)
may be directly read and written to. When accessed
through this manner, the host controller must handle all
address increment and wrap-around calculations that
may be necessary. This also includes translation from
byte to word addressing when a 16-bit PSP interface is
used.
Direct access is unavailable when the SPI interface is
used.
TRANSMIT BUFFER
DIRECT SRAM BUFFER ACCESS
the
SRAM
simultaneously.
DS39935C-page 33
The
RX