ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 112

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
When LINKIF link status change interrupt flag is set, it
means auto-negotiation or parallel detection is
complete. Once auto-negotiation is complete, the MAC
registers related to Duplex mode must be reconfigured.
Determine the new Duplex mode by reading the
PHYDPX bit (ESTAT<10>). Once this is done, update
REGISTER 12-1:
DS39935C-page 110
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-0
Note 1:
R/W-0
R/W-0
PRST
r
Applicable only when auto-negotiation is disabled (ANEN = 0 ).
PRST: PHY Reset bit
1 = Perform PHY Reset. Hardware automatically clears this bit to ‘ 0 ’ when the Reset is complete.
0 = PHY is not in Reset (normal operation)
PLOOPBK: PHY Loopback Enable bit
1 = Loopback is enabled
0 = Normal operation
SPD100: PHY Speed Select Control bit
1 = 100 Mbps
0 = 10 Mbps
ANEN: PHY Auto-Negotiation Enable bit
1 = Auto-negotiation is enabled. SPD100 and PFULDPX are ignored.
0 = Auto-negotiation is disabled. SPD100 and PFULDPX control the operating speed and duplex.
PSLEEP: PHY Sleep Enable bit
1 = PHY is powered down
0 = Normal operation
Reserved: Write as ‘ 0 ’, ignore on read
RENEG: Restart Auto-Negotiation Control bit
1 = Restart the auto-negotiation process. Hardware automatically clears this bit to ‘ 0 ’ when the
0 = Normal operation
PFULDPX: PHY Duplex Select Control bit
1 = Full duplex
0 = Half duplex
Reserved: Write as ‘ 0 ’, ignore on read
Reserved: Ignore on read
PLOOPBK
R/W-0
auto-negotiation process starts.
R-0
r
PHCON1: PHY CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
SPD100
R/W-0
R-0
r
(1)
R/W-1
ANEN
R-0
r
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PSLEEP
R/W-0
the MACON2, MACLCON, MAIPG and MABBIPG
registers as described in Section 8.9 “After Link
Establishment” .
R-0
r
R/W-0
R-0
r
r
 2010 Microchip Technology Inc.
x = Bit is unknown
RENEG
R/W-0
R-0
r
PFULDPX
R/W-0
R-0
r
bit 8
bit 0
(1)