ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 37

IC ETHERNET CTRLR W/SPI 44-QFN

ENC424J600-I/ML

Manufacturer Part Number
ENC424J600-I/ML
Description
IC ETHERNET CTRLR W/SPI 44-QFN
Manufacturer
Microchip Technology
Datasheets

Specifications of ENC424J600-I/ML

Package / Case
44-QFN
Controller Type
Ethernet Controller
Interface
SPI
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
96mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
117 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ENC424J600-I/ML
Manufacturer:
Microchip
Quantity:
1 330
For example, to read data from address 5402h of the
buffer:
1.
2.
Following the read, the EGPRDPT value normally
increments by 1 (to 5403h in this example). If the host
subsequently wants to read from address 5403h, it can
simply perform a second read from the EGPDATA
Window register. The Write Pointer, EGPWRPT, is not
affected by the read operation.
Similarly, to write A3h to address 0007h of the buffer:
1.
2.
Following the write, the EGPWRPT value normally
increments by 1 (to 0008h in this example). The Read
Pointer, EGPRDPT, is not affected by the write
operation.
Each of the three pointer sets (general purpose,
receive and user-defined area) can be used to access
any address within the SRAM buffer. They differ from
each other based on their address wrapping behavior.
Applications may choose to use all three pointer
interfaces to access the RAM. This may offer maximum
application performance as it will require minimal con-
text switching overhead when, for example, switching
from reading a received packet to reading from general
purpose
applications may prefer to use only one or two of the
three E*DATA interfaces.
EQUATION 3-1:
 2010 Microchip Technology Inc.
if EGPRDPT/EGPWRPT = ERXST – 1, then
else if EGPRDPT/EGPWRPT = 5FFFh, then
else
Write 5402h to EGPRDPT.
Read from EGPDATA.
Write 0007h to EGPWRPT.
Write A3h to EGPDATA.
RAM.
EGPRDPT/EGPWRPT = 0000h
EGPRDPT/EGPWRPT = 0000h
EGPRDPT/EGPWRPT = EGPRDPT/EGPWRPT + 1
However,
POINTER INCREMENT LOGIC FOR EGPRDPT AND EGPWRPT
for
simplicity,
some
ENC424J600/624J600
3.5.5.1
Normally, operations involving EGPDATA cause the
EGPRDPT or EGPWRPT Pointer to automatically
increment by one byte address. However, if the end of
the general purpose buffer area (ERXST – 1) is
reached, or the end of the implemented SRAM (5FFFh)
is reached, the pointer will increment to address 0000h
instead, causing subsequent accesses to wrap around
to the beginning of the SRAM buffer (Figure 3-6). The
increment behavior logic is explained in Equation 3-1.
FIGURE 3-6:
Circular Wrapping with EGPDATA
Circular RX FIFO
General Purpose
Unimplemented
CIRCULAR BUFFER
WRAPPING USING THE
EGPDATA WINDOW
Buffer
Buffer
DS39935C-page 35
0000h
ERXST – 1
ERXST
5FFFh

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