MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 94

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CM—Cache Mode
FC2—Function Code Bit 2 (Supervisor/User)
G—Global
Logical Address
M—Modified
Physical Address
MOTOROLA
This field selects the cache mode and accesses serialization as follows:
Section 5 Caches provides detailed information on caching modes.
This bit contains the function code corresponding to the logical address in this entry. FC2
is set for supervisor mode accesses and cleared for user mode accesses.
When set, this bit indicates the entry is global. Global entries are not invalidated by the
PFLUSH instruction variants that specify nonglobal entries, even when all other selection
criteria are satisfied.
This 16-bit field contains the most significant logical address bits for this entry. All 16 bits
of this field are used in the comparison of this entry to an incoming logical address when
the page size is 4 Kbytes. For 8-Kbytes pages, the least significant bit of this field is
ignored.
The modified bit is set when a valid write access to the logical address corresponding to
the entry occurs. If the M-bit is clear and a write access to this logical address is
attempted, the MC68060 suspends the access, initiates a table search to set the M-bit in
the page descriptor, and writes over the old ATC entry with the current page descriptor
information. The MMU then allows the original write access to be performed. This proce-
dure ensures that the first write operation to a page sets the M-bit in both the ATC and the
page descriptor in the translation tables, even when a previous read operation to the page
had created an entry for that page in the ATC with the M-bit clear.
The upper bits of the translated physical address are contained in this field.
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Noncachable, Precise
11 = Noncachable, Imprecise
ENTRY
TAG
*FOR 4-KBYTE PAGE SIZES, THIS FIELD USES ADDRESS BITS 31–12; FOR 8-KBYTE PAGE SIZES, BITS 31–13.
U1
V
U0
G
Figure 4-20. ATC Entry and Tag Fields
FC2
CM
M68060 USER’S MANUAL
M
LOGICAL ADDRESS*
W
PHYSICAL ADDRESS*
Memory Management Unit
4-25