MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 227

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
setup and hold times to BCLK (specifications #51 and #52 in Section 12 Electrical and
Thermal Characteristics) only if recognition by a specific BCLK rising edge is required and
for configuration settings to be registered on the rising BCLK edge shown in Figure 7-48.
TS must be pulled up or negated during reset. Once RSTI negates, the processor is inter-
nally held in reset for another 27 CLK cycles. During the reset period, all signals that can be,
are three-stated, and the remaining signals are driven to their inactive state. Once RSTI
negates, all bus signals continue to remain in a high-impedance state until the processor is
granted the bus. If BG is negated to the processor, the bus is three-stated, and no bus cycle
activity is present until BG is asserted. Afterwards, the first bus cycle for reset exception pro-
cessing begins. In Figure 7-48 the processor assumes implicit bus ownership on reset
before the first bus cycle begins. The levels on IPLx and D15–D0 are used to selectively
enable the special modes of operation when RSTI is negated. These signals are registered
into the processor on the last rising edge of BCLK in which RSTI is sampled low. These sig-
nals should be driven to their normal levels before the end of the 27-CLK internal reset
period.
7-72
IPL2–IPL0
SIGNALS
V CC
D15-D0,
+3.3 V
BCLK
RSTI
BUS
BTT
TIP
0 V
BG
TS
BR
BB
NOTE: For the processor to begin bus cycles after reset, BG must be asserted, TS must be negated or pulled up. If bus arbitration activity
is started by an alternate master (TS asserted), BTT must be asserted (or BB transition from asserted to negated) eventually to indicate
an end to the alternate master's tenure.
Figure 7-48. Initial Power-On Reset Timing
BCLK CYCLES
t 10
>
M68060 USER’S MANUAL
CLK CYCLES
27
MOTOROLA