MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 313

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.7 IMMEDIATE INSTRUCTION EXECUTION TIMES
Table 10-10 shows the number of clock cycles required for execution of the immediate
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
1
MOTOROLA
Instruction
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
MOVEQ
ADDQ
SUBQ
CMPI
EORI
ADDI
ANDI
SUBI
ORI
“
“
“
“
“
“
“
“
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Long
Long
Long
Long
Long
Long
Long
Long
Long
Size
Table 10-10. Immediate Instruction Execution Times
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
1(0/
Dn
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
1(0/
1(0/
1(0/
1(0/
An
—
—
—
—
—
—
—
—
—
—
—
—
—
0)
0)
0)
0)
(An)
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
—
1)
1)
1)
1)
1)
1)
0)
0)
1)
1)
1)
1)
1)
1)
1)
1)
M68060 USER’S MANUAL
(An)
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
—
1)
1)
1)
1)
1)
1)
0)
0)
1)
1)
1)
1)
1)
1)
1)
1)
+
–(An) (d16,An) (d8,An,Xi*SF) (bd,An,Xi*SF)
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
1(1/
—
1)
1)
1)
1)
1)
1)
0)
0)
1)
1)
1)
1)
1)
1)
1)
1)
2(1/1)
2(1/1)
1(1/1)
1(1/1)
2(1/1)
2(1/1)
2(1/0)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
1(1/1)
1(1/1)
Destination
—
1(1/1)
2(1/1)
2(1/1)
2(1/0)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
1(1/1)
1(1/1)
2(1/1)
2(1/1)
1(1/1)
—
Instruction Execution Timing
3(1/1)
3(1/1)
2(1/1)
2(1/1)
3(1/1)
3(1/1)
3(1/0)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
2(1/1)
2(1/1)
—
1
(xxx).WL
2(1/1)
2(1/1)
1(1/1)
1(1/1)
2(1/1)
2(1/1)
2(1/0)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
1(1/1)
1(1/1)
—
10-17