MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 337

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.2.8 Miscellaneous Pullup Resistors
Pullup CLA to prevent the A3 and A2 address lines from cycling on burst accesses. Pullup
TRA when MC68040 acknowledge termination mode is being used.
11.3 EXAMPLE DRAM ACCESS
When interfacing the MC68060 with dynamic random access memory (DRAM), it is neces-
sary to determine how many clocks per bus cycle will be needed for a line burst transfer.
The number of clocks per bus cycle is dependent upon the processor clock frequency and
the DRAM access times. In this example, the DRAM RAS access time, CAS access time,
RAS precharge time, and CAS precharge time are used to determine the number of clocks
per bus cycle of a DRAM access. Figure 11-11 shows two successive line burst transfers.
The CLA signal is used to cycle A3 and A2 a clock before the DRAM subsystem asserts TA.
MOTOROLA
DRAM ADDRESS
(WRITE CYCLE)
(READ CYCLE)
A3–A2
DATA
DATA
RAS
CAS
CLK
CLA
TS
TA
Figure 11-10. MC68040 BCLK to CLKEN Relationship
ROW
W0
C0
Figure 11-11. DRAM Timing Analysis
CLKEN
W1
BCLK
C1
CLK
M68060 USER’S MANUAL
W2
C2
W3
C3
ROW
W0
C0
W1
C1
Applications Information
W2
C2
W3
C3
11-15