MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 347

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12.7 INPUT AC TIMING SPECIFICATIONS (V
NOTE:
MOTOROLA
Num
22a TA, Valid to BCLK (Setup)
22b TEA Valid to BCLK (Setup)
22d TBI Valid to BCLK (Setup)
22e TRA Valid to BCLK (Setup)
41a BB Valid to BCLK (Setup)
41b BG Valid to BCLK (Setup)
41d IPL » Valid to CLK (Setup)
41e BTT Valid to BCLK (Setup)
42a BCLK to BB Invalid (Hold)
42b BCLK to BG Invalid (Hold)
42d CLK to IPLx Invalid (Hold)
42e BCLK to BTT Invalid (Hold)
44a Address Valid to BCLK (Setup)
44e SNOOP Valid to BCLK (Setup)
45a BCLK to Address Invalid (Hold)
45e BCLK to SNOOP Invalid (Hold)
22c TCI Valid to BCLK (Setup)
41c CDIS, MDIS Valid to BCLK (Setup)
42c BCLK to CDIS, MDIS Invalid (Hold)
44c TT1 Valid to BCLK (Setup)
45c BCLK to TT1 Invalid (Hold)
41f BGR Valid to BCLK (Setup)
42f BCLK to BGR Invalid (Hold)
15
16
17
23
24
25
46
47
49
51
52
53
54
64
65
BCLK is not a pin signal name. It is a virtual bus clock where the BCLK rising edge coincides with that of CLK when
CLKEN is asserted. The BCLK falling edge is insignificant. An input timing reference to BCLK means that the specific
input transitions only on rising CLK edges when CLKEN is asserted. A timing reference to CLK means that the input
may transition off the rising CLK edge, regardless of CLKEN state.
Data-In Valid to BCLK (Setup)
BCLK to Data-In Invalid (Hold)
BCLK to Data-In High Impedance
(Read Followed by Write)
BCLK to TA, TEA, TCI, TBI, TRA Invalid
(Hold)
AVEC Valid to BCLK (Setup)
BCLK to AVEC Invalid (Hold)
TS Valid to BCLK (Setup)
BCLK to TS Invalid (Hold)
BCLK to BB in High Impedance
(MC68060 Assumes Bus Mastership)
RSTI Valid to BCLK
BCLK to RSTI Invalid (hold)
Mode Select Setup to BCLK (RSTI Asserted)
BCLK to Mode Selects Invalid (RSTI Assert-
ed)
CLA Valid to BCLK (Setup)
BCLK to CLA Invalid (Hold)
Characteristic
M68060 USERÕS MANUAL
Min
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Ñ
Ñ
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
50 MHz
Max
11
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
3
CC
Min
Ñ
Ñ
Electrical and Thermal Characteristics
2
2
7
7
7
7
7
2
7
2
7
7
7
2
7
7
2
2
2
2
2
2
1
7
7
2
2
2
7
2
2
2
7
2
7
2
66 MHz
= 3.3 V ± 5%)
Max
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
9
3
Min.
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
6.2
Ñ
Ñ
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
75 MHz
Max.
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
8
3
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
12-5