MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet
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MC68EC060RC66
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... Freescale Semiconductor, Inc. Microprocessor and Memory Technologies Group Product Brief Superscalar 32-Bit Microprocessors The superscalar M68060 represents a new line of Motorola microprocessor products. The first generation of the M68060 product line consists of the MC68060, MC68LC060, and MC68EC060. All three microprocessors offer superscalar integer performance of over 100 MIPS at 66 MHz. The MC68060 comes fully equipped with both a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control and desktop applications ...
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... Freescale Semiconductor, Inc. Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architectural techniques, the MC68060 harnesses new levels of performance for the M68000 family. Incorporating 2.5 million transistors on a single piece of silicon, the MC68060 employs a deep pipeline, dual ...
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... Freescale Semiconductor, Inc. The following is a list of primary featuresof the MC68060: • Fully User-Code Compatible with MC68040 • Superscalar Implementation of M68000 Architecture — Dual Integer Instruction Execution Improves Performance • Branch Cache Reduces Branches to Zero Cycles • Executes Three Instructions per Clock • ...
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... Freescale Semiconductor, Inc. Figure 2 shows the MC68060 functional signal groups. A31–A0 ADDRESS BUS AND CONTROL CLA D31–D0 DATA BUS TT1 TT0 TM2 TM1 TM0 TLN1 TLN0 UPA1 UPA0 TRANSFER R/W ATTRIBUTES SIZ1 SIZ0 LOCK LOCKE CIOUT BS0 BS1 BS2 ...
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... Freescale Semiconductor, Inc. The MC68060 execution unit carries out logical and arithmetic operations. The execution unit contains an instruction fetch unit, an integer unit, a branch cacheand a floating-point unit. The superscalar design of the MC68060 provides dual execution pipelines in the instruction integer unit, providing simultaneous instruction execution ...
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... Freescale Semiconductor, Inc. The integer unit control logic pulls an instruction pair from the instruction buffer every machine clock cycle, stopping only if the instruction information is not available integer execution pipeline hold condition ex- ists. The six stages in the dual integer execution pipelines are: 1) Instruction Decode— ...
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... Freescale Semiconductor, Inc. MEMORY MANAGEMENT UNITS (MC68060 AND MC68LC060 ONLY) The MC68060 contains independent instruction and data MMUs. Each MMU contains a cache memory called the address translation cache (ATC). The full addressing range of the MC68060 is four Gbytes (4,294,967,296 bytes). Even though most MC68060 systems implement a much smaller physical memory, by using virtual memory techniques, the system can appear to have a full four Gbytes of physical memory available to each user program ...
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... Freescale Semiconductor, Inc. CACHE ORGANIZATION The instruction and data caches are each organized as four-way set associative, with 16-byte lines. Each line of data has associated with it an address tag and state information that shows the line’s validity. In the data cache, the state information indicates whether the line is invalid, valid, or dirty. ...
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... Freescale Semiconductor, Inc. POWER MANAGEMENT The MC68060 is very power efficient due to the static logic and power management designed into the basic architecture. Each stage of the integer unit pipelines and the FPU pipeline draws power only when an instruction is executing, and the cache arrays draw power only when an access is made. The FPU, secondary integer execution pipeline, branch cache, and instruction and data caches can be disabled to reduce overall power usage. The 3.3-V power supply reduces current consumption by 40– ...
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... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...