MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 188

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

and debounce these signals. An interrupt request that is held constant for two consecutive
CLK periods is considered a valid input. Although the protocol requires that the request
remain until the processor runs an interrupt acknowledge cycle for that interrupt value, an
interrupt request that is held for as short a period as two CLK cycles can be potentially rec-
ognized. Figure 7-25 is a flowchart of the procedure for a pending interrupt condition.
The MC68060 asserts IPEND when an interrupt request is pending. Figure 7-26 illustrates
the assertion of IPEND relative to the assertion of an interrupt level on the IPLx signals.
IPEND signals external devices that an interrupt exception will be taken at an upcoming
MOTOROLA
DRAM ADDRESS
(WRITE CYCLE)
(READ CYCLE)
A3–A2
DATA
DATA
CLK
CLA
RAS
CAS
TS
TA
Figure 7-24. Using CLA in a High-Speed DRAM Design
OTHERWISE
Figure 7-25. Interrupt Pending Procedure
ROW
W0
M68060 USER’S MANUAL
C0
SAMPLE AND SYNCHRONIZE
ASSERT IPEND
IPL2–IPL0
W1
C1
RESET
INTERRUPT LEVEL I2–I0,
OR TRANSITION ON LEVEL 7
W2
C2
>
W3
C3
W0
C0
Bus Operation
7-33