MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 240

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Exception Processing
For all instruction traps other than TRAP #n, a stack frame of type 2 is generated. The
stacked PC contains the logical address of the next instruction to be executed. In addition
to the stacked PC, a pointer to the instruction that caused the trap is saved in the address
field of the stack frame. Instruction execution resumes at the address in the exception vector
after the required instruction is prefetched.
8.2.4 Illegal Instruction and Unimplemented Instruction Exceptions
There are eight unimplemented instruction exceptions: unimplemented integer, unimple-
mented effective address, unimplemented A-line, unimplemented F-line, floating-point dis-
abled, floating-point unimplemented instruction, floating-point unsupported data type, and
illegal instruction.
The unimplemented integer exception corresponds to vector number 61 and occurs when
the processor attempts to execute an instruction that contains a quad word operand (MULx
producing a 64-bit product and DIVx using a 64-bit dividend), CAS2, CHK2, CMP2, CAS
with a misaligned operand, and the MOVEP instruction. A stack frame of type 0 is generated
when this exception is reported. The stacked PC points to the logical address of the unim-
plemented integer instruction that caused the exception.
The unimplemented effective address exception corresponds to vector number 60, and
occurs when the processor attempts to execute any floating-point instruction that contains
an extended precision immediate source operand (F<op>, #imm,FPx), when the processor
attempts to execute an FMOVEM.L #imm,<control register list> instruction of more than one
floating-point control register (FPCR, FPSR, FPIAR), when the processor attempts an
FMOVEM.X instruction using a dynamic register list (FMOVEM.X Dn,<ea> or FMOVEM.X,
<ea>,Dn). The stack frame of type 0 is generated when this exception is reported. The
stacked PC points to the logical address of the instruction that caused the exception. The
FPIAR is unaffected. Refer to Section 6 Floating-Point Unit for details.
An unimplemented A-line exception corresponds to vector number 10 and occurs when an
instruction word pattern begins (bits 15–12) with $A. The A-line opcodes are user-reserved,
and Motorola will not use any A-line instructions to extend the instruction set of any of Motor-
ola’s processors. A stack frame of format 0 is generated when this exception is reported.
The stacked PC points to the logical address of the A-line instruction word.
A floating-point unsupported data type exception occurs when the processor attempts to
execute a bit pattern that it recognizes as an MC68881 instruction, the floating-point unit
(FPU) is enabled via the processor configuration register (PCR), the floating-point instruc-
tion is implemented, but the floating-point data type is not implemented in the MC68060
FPU. This exception corresponds to vector number 55. A stack frame of type 0, 2, or 3 is
generated when this exception is reported. The stacked PC points to the logical address of
next instruction after the floating-point instruction. Refer to Section 6 Floating-Point Unit
for details.
A floating-point unimplemented instruction exception occurs when the processor attempts
to execute an instruction word pattern that begins with $F, the processor recognizes this bit
pattern as an MC68881 instruction, the FPU is enabled via the PCR, but the floating-point
instruction is not implemented in the MC68060 FPU. This exception corresponds to vector
8-8
M68060 USER’S MANUAL
MOTOROLA