MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 323

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 11
APPLICATIONS INFORMATION
This section describes various applications topics relating to the MC68060.
11.1 GUIDELINES FOR PORTING SOFTWARE TO THE MC68060
The following paragraphs describe the issues involved in using the MC68060 in an existing
MC68040 system from a software perspective. Although this section focuses on the
MC68060, many of these items apply also to the MC68EC060 and MC68LC060.
11.1.1 User Code
The MC68060 is 100% user-mode compatible with the MC68040 when utilized with the
MC68060 software package (M68060SP) provided by Motorola. The M68060SP is available
free of charge. Appendix C MC68060 Software Package discusses the procedure for port-
ing the M68060SP.
All user-mode instructions are handled in the M68060SP, except the “TRAPF #immediate”
instruction, in which the immediate value is a valid branch opcode. Use of this construct
results in a branch prediction error and an access error exception is taken. This exception
is indicated by the BPE bit in the fault status long word (FSLW). Although this error is recov-
erable in the access error handler by flushing the branch cache, performance is compro-
mised.
In addition, the CAS (misaligned operands) and CAS2 emulation may need special handling
in the access error handler. Furthermore, CAS and CAS2 emulation must not be interrupted
by level 7 interrupts to prevent data corruption. Refer to Appendix C MC68060 Software
Package for additional information.
11.1.2 Supervisor Code
Unlike the MC68040, the MC68060 implements a single supervisor stack. System software
that requires the use of two supervisor stacks can still do so, but with some software over-
head.
The MC68060 aids in distinguishing between an interrupt exception and a non-interrupt
exception by implementing the M-bit in the status register (SR). The MC68060 does not
internally use the M-bit, but it is provided for system software. The MC68060 clears the M-
bit of the SR when an interrupt exception is taken. Otherwise, it is up to the system software
to set the M-bit and to examine it as needed. Also note, when the MC68060 takes an excep-
tion, a minimum of one instruction is always processed before a pending interrupt is taken.
MOTOROLA
M68060 USER’S MANUAL
11-1