MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 260

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Exception Processing
Once the write buffers (push and store) are all empty, the pipeline re-evaluates the pending
exception types. If no TEA fault occurred during the emptying of the buffers, the processor
continues with the original exception. If a TEA fault did occur as the buffers were emptied,
the original exception is discarded and an operand data access error exception is taken. The
exception stack for the access error includes indicator bits in the FSLW signalling the occur-
rence of the push buffer TEA or store buffer TEA. Note that both errors may be present
within a single access error exception. The exception stack frame will record the PC value
at the time the exception was detected, but this value has no relationship to the instruction
that caused the push or store buffer entries to originally be made. The stacked virtual
address is meaningless for these two fault types.
There are other non-recoverable write cases which are unrelated to the push and store
buffer cases. The execution of a misaligned read-modify-write instruction which partially
completes the writes before faulting is inherently non-recoverable on a restart machine.
Consider the ADD D0, <mem> instruction. In this instruction, the processor fetches the
memory operand, adds the contents of D0 internally, and writes the result out to memory. If
the memory operand is misaligned and a bus error occurs on the second or later access,
the first part of the memory operand would have been overwritten. If the instruction enters
the access error exception handler, it cannot be restarted because original memory value
has been corrupted. This read-modify-write instruction and others like it can be detected in
the access error handler because the access error frame has separate read and write bits
(RW field). If both bits are set, the instruction is a read-modify-write instruction similar to the
ADD instruction case as discussed.
Another non-recoverable write case is similar to the ADD case above, but is more difficult to
detect. A MOVE <mem>, <mem> instruction in which the source operand and destination
operand overlap may have the same problems as discussed in the ADD instruction if the
destination operand is part of the source operand and a misaligned write occurs, which
result in an access error on the second or later misaligned case. The MOVE <mem>,
<mem> instruction is not normally considered a read-modify-write type of instruction, and is
not detected simply by looking at the RW bits in the FSLW.
An MC68060 system design could implement address/data capture logic to provide addi-
tional information for these bus error scenarios.
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M68060 USER’S MANUAL
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