MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 52

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Signal Description
2.3.3 Transfer Line Number (TLN1, TLN0)
These three-state outputs indicate which line in the set of four data or instruction cache lines
is being accessed for normal push and line data read accesses. TLNx signals are undefined
for all other accesses and are placed in a high-impedance state when the processor is not
the bus master.
The TLNx signals can be used in high-performance systems to build an external snoop filter
with a duplicate set of cache tags. The TLNx signals and address bus provide a direct indi-
cation of the state of the data caches and can be used to help maintain the duplicate tag
store. The TLNx signals do not indicate the correct TLN number when an instruction cache
burst fill occurs.
2.3.4 User-Programmable Page Attributes (UPA1, UPA0)
The UPAx signals are three-state outputs. These signals are only valid for normal code,
data, and MOVE16 accesses. For all other accesses (including table search and cache line
push accesses), the UPAx signals are low. When the MC68060 is not the bus master, these
signals are placed in a high-impedance state.
During normal and MOVE16 accesses, if a transparent translation register (TTR) is enabled
and the address and attributes match the TTR values, the UPAx signals are defined by the
logical values of the U1 and U0 bits the TTR. If the MMU is enabled via the translation control
register (TCR) and the address and attributes result in an address translation cache (ATC)
hit, the UPAx signals are defined by the logical values of the U1 and U0 bits in the ATC entry.
If a given logical address is not mapped by the TTRs and if address translation is disabled,
2-6
Table 2-3. Normal and MOVE16 Access TMx Encoding
*MOVE16 accesses use only these encodings.
TM2
TM2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 2-4. Alternate Access TMx Encoding
TM1
TM1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M68060 USER’S MANUAL
TM0
TM0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Cache Push Access
User Data Access*
User Code Access
MMU Table Search Data Access
MMU Table Search Code Access
Supervisor Data Access*
Supervisor Code Access
Reserved
Logical Function Code 0
Debug Access
Reserved
Logical Function Code 3
Logical Function Code 4
Debug Pipe Control Mode Access
Debug Pipe Control Mode Access
Logical Function Code 7
Transfer Modifier
Transfer Modifier
MOTOROLA