MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 135

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

tests that set the BSUN bit in the FPSR status byte if an unordered condition is present when
the conditional test is attempted (IEEE nonaware tests), and 16 tests that do not cause the
BSUN bit in the FPSR status byte (IEEE aware tests). The set of IEEE nonaware tests is
best used:
An unordered condition occurs when one or both of the operands in a floating-point compare
operation is a NAN. The inclusion of the unordered condition in floating-point branches
destroys the familiar trichotomy relationship (greater than, equal, less than) that exists for
integers. For example, the opposite of floating-point branch greater than (FBGT) is not float-
ing-point branch less than or equal (FBLE). Rather, the opposite condition is floating-point
branch not greater than (FBNGT). If the result of the previous instruction was unordered,
FBNGT is true; whereas, both FBGT and FBLE would be false since unordered fails both of
these tests. Compiler programmers should be particularly careful of the lack of trichotomy in
the floating-point branches since it is common for compilers to invert the sense of conditions.
When using the IEEE nonaware tests, the BSUN bit and the NAN bit are set in the FPSR,
unless the branch is an FBEQ or an FBNE. If the BSUN exception is enabled in the FPCR,
an exception is taken. Therefore, the IEEE nonaware program may be interrupted if an
unexpected condition occurs.
Compilers and programmers who are knowledgeable of the IEEE 754 standard should use
the IEEE aware tests in programs that contain ordered and unordered conditions. Since the
ordered or unordered attribute is explicitly included in the conditional test, the BSUN bit is
not set in the FPSR EXC byte when the unordered condition occurs.
Table 6-9 summarizes the conditional mnemonics, definitions, equations, predicates, and
whether the BSUN bit is set in the FPSR EXC byte for the 32 floating-point conditional tests.
The equation column lists the combination of FPCC bits for each test in the form of an equa-
tion.
MOTOROLA
• When porting a program from a system that does not support the IEEE 754 standard to
• When generating high-level language code that does not support IEEE floating-point
a conforming system, or
concepts (i.e., the unordered condition).
M68060 USER’S MANUAL
Floating-Point Unit
6-17