MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 164

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.6 MISALIGNED OPERANDS
All MC68060 data formats can be located in memory on any byte boundary. A byte operand
is properly aligned at any address, a word operand is misaligned at an odd address, and a
long word is misaligned at an address that is not evenly divisible by four. However, since
operands can reside at any byte boundary, they can be misaligned. Although the MC68060
does not enforce any alignment restrictions for data operands (including program counter
(PC) relative data addressing), some performance degradation occurs when additional bus
cycles are required for long-word or word operands that are misaligned. For maximum per-
formance, data items should be aligned on their natural boundaries. All instruction words
and extension words must reside on word boundaries. Attempting to prefetch an instruction
word at an odd address causes an address error exception. Refer to Section 8 Exception
Processing for details on address error exceptions.
The MC68060 data memory unit converts misaligned operand accesses that are noncach-
able to a sequence of aligned accesses. These aligned accesses are then sent to the bus
controller for completion, always resulting in aligned bus transfers. Misaligned operand
accesses that miss in the data cache are cachable and are not aligned before line filling.
Refer to Section 5 Caches for details on line fill and the data cache.
MOTOROLA
NOTES
TT1, TT0
A31–A0
LOCKE
CIOUT
UPA1,
Signal
TLN1,
LOCK
UPA0
TM2–
SIZ1,
TLN0
1) The UPA1, UPA0, and CIOUT signals are determined by the U1, U0, and CM bit fields, respectively,
2) The TLNx signals are defined only for normal push accesses and normal data line read accesses.
3) The LOCK signal is asserted during TAS and CAS operand accesses and for some table search update
4) Refer to Section 2 Signal Description for definitions of the TMx signal encoding for normal, MOVE16, and
SIZ0
TM0
Bus
R/W
corresponding to the access address.
sequences. LOCKE is asserted for the last bus cycle of a locked sequence of bus cycles. LOCK and LOCKE
may also be asserted after the execution of a MOVEC instruction that sets the L or LE bit, respectively, in the
BUSCR (see 7.4 Bus Control Register ).
alternate accesses.
Cache Set
Negated
Negated
Address
Access
Access
Cache
L/Line
Push
Entry
Write
Data
$0
$0
$0
Table 7-2. Summary of Access Types vs. Bus Signal Encoding
$1,2,5, or 6
Read/Write Read/Write Read/Write Read/Write
B/W/L/Line Long Word
Cache Set
Negated 3
Asserted/
Address
Source 1
Source 1
Access
Normal
Access
Entry 2
Data/
Code
MMU
MMU
$0
Undefined
Negated 3
Asserted/
Negated
Address
Access
Search
$3 or 4
Table
Entry
$0
$0
M68060 USER’S MANUAL
Undefined
MOVE16
Negated
Address
Source 1
Source 1
Access
Access
$1 or 5
MMU
MMU
Line
$1
Code=0,3,
Undefined
Alternate
Asserted
Function
Access=
Negated
Address
Access
Access
Debug
B/W/L
1,5,6
4,7
$0
$2
Int. Level $1–7
Acknowledge
$FFFFFFFF
Undefined
Interrupt
Negated
Negated
Read
Byte
$0
$3
$FFFFFFFE
Broadcast
Undefined
LPSTOP
Negated
Negated
Cycle
Word
Write
$0
$3
$0
Bus Operation
Acknowledge
Breakpoint
$00000000
Undefined
Negated
Negated
Read
Byte
$0
$3
$0
7-9