MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 214

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
and then three-states BTT. If the external bus arbiter has granted the bus to an alternate
master by the assertion of BG to that master, that master, using this protocol, can start a bus
cycle on the rising BCLK edge in which it detects the assertion of BTT. The previous master
can be driving BTT negated at the same time the current master is starting a bus cycle
because the current master will still have its BTT signal three-stated. Since the alternate
master does not drive BTT in this protocol until it has finished its tenure, there is no conflict
with tying all master’s BTT signals together. This is different than the MC68040-arbitration
protocol which used BB to continuously indicate to other bus masters the bus was being
used by the MC68040.
When a processor using the MC68040-arbitration protocol is finished using the bus, BB has
to be driven negated for a short period of time and then three-stated. The use of the BTT
protocol works much better than the BB protocol in a high-speed bus environment because
the kind of drive (asserted, negated, or three-stated) of BTT can be synchronous with the
clock. Arbiters do not need to be changed going from a MC68040 system to a MC68060 sys-
tem, since arbiters do not need to sample the BB signal in a MC68040 system or BTT in a
MC6060 system, but need only use BR, BG, and perhaps LOCK to determine bus owner-
ship rights. Masters need only sample BB or BTT and TS and BG to determine the proper
times to take over ownership of the bus. In cases where the MC68060 has implicit bus own-
ership after it has finished all needed bus cycles, BTT remains three-stated until BG is
negated and the MC68060 is forced off the bus. For this case, in the next BCLK period after
the MC68060 detects the negation of BG, it asserts BTT for one BCLK period, negates BTT
for one BCLK period, and then three-states BTT. In implicit bus ownership cases where the
MC68060 is given the bus but never actually uses it by asserting TS, the MC68060 does not
assert BTT when BG is negated.
In systems that use the BTT protocol, the assertions of TS and BTT must be tracked by mas-
ters, to determine the proper times at which the bus may be taken over. Assertions of BTT
prior to, during, and after the negation of BG may also need to be logged by a master in
cases where the BG is not parked with a master and no master has used the bus for some
time. In such cases the master is required to have kept state information that indicated a pre-
vious master had earlier finished using the bus, implying it is safe to immediately take control
of the bus. The MC68060 processor internally maintains this information.
After external reset, initiated with the negation of RSTI, and with BG asserted, the MC68060
does not wait for the assertion of BTT by another master to take over mastership of the bus
and start bus activity, provided there has been no assertion of TS by another master in the
interim of time between the negation of RSTI and the clock cycle when the MC68060 is
ready to start a bus cycle. If another master starts bus activity (TS asserted) in this interim
of time, even though the MC68060 may have received a bus grant indication (BG asserted),
the MC68060 waits for BTT to be asserted by the other master before it takes over bus mas-
tership.
When BG is negated by the arbiter, the MC68060 relinquishes the bus as soon as the cur-
rent bus cycle is complete unless a locked sequence of bus cycles is in progress with BGR
negated. In this case, the MC68060 completes the sequence of atomic locked bus cycles,
drives LOCK and LOCKE negated for one BCLK period during the clock when the address
and other bus cycle attributes are idled, and in the next BCLK period, three-states LOCK
MOTOROLA
M68060 USER’S MANUAL
7-59