MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 401

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPUSH
Operation:
Assembler
Syntax:
Attributes:
Description:
MOTOROLA
instruction cache, both caches, or neither cache can be specified. When the data
cache is specified, the selected data cache lines are first pushed to memory (if they
contain dirty data) and then invalidated if the DPI bit of the CACR is cleared. Otherwise,
the selected data cache lines remain valid. Selected instruction cache lines are invali-
dated. The CACR is accessed via the MOVEC instruction.
Specific cache lines can be selected in three ways:
1. CPUSHL pushes and possibly invalidates the cache line (if any) matching the
2. CPUSHP pushes and possibly invalidates the cache lines (if any) matching the
3. CPUSHA pushes and possibly invalidates all cache entries.
physical address in the specified address register.
physical memory page in the specified address register. For example, if 4K-byte
page sizes are selected and An contains $12345000, all cache lines matching
page $12345000 are selected.
If Supervisor State, Then
Endif
Else TRAP
CPUSHL<caches>,(An)
CPUSHP<caches>,(An)
CPUSHA<caches>
Where <caches> specifies the instruction cache, data
cache, both caches, or neither cache.
Unsized
Pushes and possibly invalidates selected cache lines. The data cache,
If Data Cache, Then
Endif
If Instruction Cache, Then
Endif
Push Selected Dirty Data Cache Lines
If DPI bit of CACR = 0, Then
Endif
Invalidate Selected Cache lines
Push and Possibly Invalidate Cache Line
(MC68060, MC68LC060, MC68EC060)
Invalidate Selected Cache Lines
M68060 USER’S MANUAL
MC68060 Instructions
CPUSH
D-11