MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 73

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
4.1.2 Translation Control Register
The 32-bit TCR contains control bits which select translation properties. The operating sys-
tem must flush the ATCs before enabling address translation since the TCR accesses and
reset do not flush the ATCs. All unimplemented bits of this register are read as zeros and
must always be written as zeros. The MC68060 always uses long-word transfers to access
this 32-bit register. All bits are cleared by reset. Figure 4-4 illustrates the TCR.
Bits 31–16—Reserved by Motorola. Always read as zero.
E—Enable
P—Page Size
NAD—No Allocate Mode (Data ATC)
NAI—No Allocate Mode (Instruction ATC)
FOTC—1/2-Cache Mode (Data ATC)
4-4
31
0
This bit enables and disables paged address translation.
A reset operation clears this bit. When translation is disabled, logical addresses are used
as physical addresses. The MMU instruction, PFLUSH, can be executed successfully
despite the state of the E-bit. If translation is disabled and an access does not match a
transparent translation register (TTR), the default attributes for the access on the TTR is
defined by the DCO, DUO, DCI, DWO, DUI (default TTR) bits in TCR.
This bit selects the memory page size.
This bit freezes the data ATC in the current state, by enforcing a no-allocate policy for all
accesses. Accesses can still hit, misses will cause a table search. A write access which
finds a corresponding valid read will update the M-bit and the entry remains valid.
This bit freezes the instruction ATC in the current state, by enforcing a no-allocate policy
for all accesses. Accesses can still hit, misses will cause a table search.
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 = Disable
1 = Enable
0 = 4 Kbytes
1 = 8 Kbytes
0 = Disabled
1 = Enable
0 = Disabled
1 = Enable
0 = The data ATC operates with 64 entries.
1 = The data ATC operates with 32 entries.
Figure 4-4. Translation Control Register Format
16
0
M68060 USER’S MANUAL
15
E
14
P
NAD
13
NAI
12
FOTC
11
FITC
10
9
DCO
8
7
DUO
6
DWO
5
MOTOROLA
4 3 2 1 0
DCI
DUI
0