MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 378

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Finally, if the result of the floating-point multiplication unit is a normalized extended-precision
number with a zero exponent, then the processor will incorrectly take an underflow excep-
tion. The M68060SP detects and corrects this case.
C.3.2.3.2 Signalling Not-A-Number, Operand Error. On the MC68060, the signalling not-
a-number (SNAN) and operand error (OPERR) exceptions cause pre-instruction exceptions
for opclass zero and two instructions and post-instruction exceptions for opclass three
instructions. The processor takes exception vector number fifty-four for the SNAN exception
and vector number fifty-two for the OPERR exception. The FSAVE frames for the exceptions
are valid and contain the source operands converted to extended precision.
SNAN and OPERR were non-maskable exceptions on the MC68040 for opclass three
instructions with byte, word, or long-word destination formats. The exceptions were non-
maskable so that the MC68040FPSP software could provide the default SNAN or OPERR
results when the exceptions were disabled. With the MC68060, as with the MC68881/882,
SNAN and OPERR are entirely maskable since the default trap disabled results are pro-
vided by floating-point hardware.
MOTOROLA
• Floating-point data register destination:
—exception stack frame: the four-word pre-instruction stack frame contains the
—in the FSAVE frame: the exceptional operand which is the intermediate result
—at the destination location: the default underflow/overflow result.
—FPIAR: address of the instruction that underflowed/overflowed.
—FPSR: the bits are set according to the default result.
PC of the next instruction.
mantissa rounded to extended precision, with an exponent bias of
$3FFF+$6000 for underflow and $3FFF-$6000 for overflow rather than $3FFF.
In cases of catastrophic overflow/underflow, the exceptional operand exponent
is set to $0000. The user ovfl/unfl handler must execute an FSAVE to retrieve
this value.
Unlike the MC68040, the MC68060 FPU hardware does not pro-
vide the exceptional operand on overflow or underflow for use by
an exception handler. Therefore, the M68060FPSP overflow
and underflow handlers must emulate the entire faulted instruc-
tion in order to calculate the exceptional operand for the user en-
abled overflow or underflow handler.
M68060 USER’S MANUAL
Note
MC68060 Software Package
C-17