MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 29

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Architectural highlights of the MC68060 include:
This pipeline architecture supports extremely high data transfer rates within the MC68060
processor. The on-chip instruction and operand data caches provide 600 MBytes/sec @ 50
MHz to the pipelines, while the integer execute engines can support sustained transfer rates
of 1.2 GBytes/sec.
1.4 PROCESSOR OVERVIEW
The following paragraphs provide a general description of the MC68060.
1.4.1 Functional Blocks
Figure 1-1 illustrates a simplified block diagram of the MC68060.
MOTOROLA
• Four-Stage Instruction Fetch Unit (IFU)
• Four-Stage Execution Pipelines Featuring Primary Pipeline (pOEP), Secondary Pipe-
— 64-Entry Instruction Address Translation Cache (ATC), Organized as 4-Way Set-
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache
—256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache, Which Predicts
—96-Byte FIFO Instruction Buffer to Allow Decoupling of the IFP and OEPs
line (sOEP), and Register File (RGF) Containing Program-Visible General Registers
— 64-Entry Operand Data ATC, Organized as 4-Way Set-Associative, for Fast Virtual-
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Operand Data Cache
— The Operand Data Cache Is Organized in a Banked Structure to Allow Simultaneous
— Integer Execute Engines Optimized to Perform Most Instruction Executions in a
—Floating-Point Execute Engine, with Floating-Point Register File, Optimized for Per-
—Four-Entry Store Buffer and One-Entry Push Buffer That Provide the Performance
Associative, for Fast Virtual-to-Physical Address Translations
the Direction of Branches Based on Their Past Execution History
to-Physical Address Translations
Read/Write Accesses
Single Machine Cycle
formance with Extended-Precision-Wide Internal Datapaths.
Feature of Decoupling the Processor Pipeline from External Memory for Certain
Cache Modes of Operation.
M68060 USER’S MANUAL
Introduction
1-5