IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 84

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–58
3.8.2. MAC Only Clocks
Figure 3–32. MAC Only Clocks
10-Gbps Ethernet IP Functional Description
1
avl_st_tx_clk
Avalon-ST Tx IF
Avalon-ST Rx IF
sysclk
avalon addr & data
avalon_clk
In this configuration the application logic provides the clock for the MAC and MAC
side of the FIFO logic.
The reset connections for
in
Figure 3–32
Avalon-ST clock domain (avl_st_tx_clk or avl_st_rx_clk)
Avalon-MM clock domain (avalon_clk)
Sysclk domain (sysclk)
Altera FPGA
for clarity.
FIFO
FIFO
Wr
Wr
Interface
Avalon
FIFO
FIFO
Rd
Rd
Figure 3–32
are the same as in
MAC Rx
MAC Tx
Sync
Dynamic register bits (sysclk)
Interface
XGMII
Figure
Static register bits
© July 2010 Altera Corporation
3–31. The are omitted
Clocks and Reset