IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 60

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–34
Table 3–16. Control Interface Register Map (Part 3 of 7)
10-Gbps Ethernet IP Functional Description
0x03C
0x040
0x044
–
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
Address
Offset
mdio_addr0
Unused
Reserved
Reserved
tx_ipg_length
aMacID
aFramesTransmittedOK_0 See
aFramesReceivedOK_0
aFrameCheckSequence
Errors
aAlignmentErrors
aOctetsTransmittedOK_0 See
aOctetsReceivedOK_0
aTxPAUSEMACCtrlFrames
aRxPAUSEMACCtrlFrames
ifInErrors
ifOutErrors
ifInUcastPkts
ifInMulticastPkts
ifInBroadcastPkts
ifOutDiscards
ifOutUcastPkts
ifOutMulticastPkts
ifOutBroadcastPkts
Name
MDIO address of PHY device 0.
■
■
■
Unused.
Reserved.
Reserved.
Minimum IPG. Valid values are 8–252
bytes. If this register is set to an
invalid value, it defaults to 12
byte-times which is a typical value of
minimum IPG. Bits 5–31 are reserved
and set to read-only value 0.
This register is wired to mac_0 and
mac_1 addresses respectively.
See
See
See
See
See
See
See
See
See
See
See
See
See
See
See
4:0 are the PHY address (clause
22) or the device address (clause
45)
12:8 are the port address (clause
45 only)
31:16 are the register address
(clause 45 only). To read and write
for clause 45, the read and write
must be done at address 0x320
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–18 on page
Table 3–19 on page
Table 3–19 on page
Table 3–19 on page
Table 3–19 on page
Table 3–19 on page
Table 3–21 on page
Table 3–19 on page
Table 3–19 on page
Table 3–19 on page
Description
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–41.
3–43.
3–41.
3–41.
3–41.
Access
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
© July 2010 Altera Corporation
HW Reset
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Descriptions
SW Reset
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0