IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 66

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–40
Table 3–17. Command_Config Register Bit Descriptions (Part 3 of 3)
3.6.2. Software Reset
3.6.3. Statistics Block
3.6.4. IEEE 802.3 Management Packages
10-Gbps Ethernet IP Functional Description
Bit(s)
27
28
29
30
31
LINE_LOOP_ENA
BROAD_FILTER_
ENA
INS_CRC_ERR
NO_PAUSE_FIFO
CNT_RESET
Bit Name
A software application can reset the IP core by setting the SW_RESET bit in the
command_config register to 1. During a software reset, the IP core clears all statistics
registers, flushes both the Tx and Rx FIFOs, and disables the transmitter and receiver
by setting the TX_ENA and RX_ENA bits in the command_config register to 0.
The value of configuration registers, such as the address and FIFO thresholds are
preserved. The SW_RESET bit is cleared automatically when the software reset ends.
For more information about the reset signal, refer to
page
The statistics block accumulates statistics required in IEEE802.3 Basic, Mandatory and
Recommended Management Information Packages, IEEE 802.3ah, Clause 30.
In addition, the IP core provides all signals to generate the applicable objects of the
Management Information Base (MIB, MIB-II) according to IETF RFC2665 and Remote
Network Monitoring (RMON) according to IETF RFC 2819 for SNMP Managed
Environments.
The statistics block implements the applicable parts of the RMON (RFC 2819), MIB
(RFC 3635), and MIB (RFC 2863). The sections and tables below describe in detail the
statistics counters that were listed in
to which they belong.
Table 3–18
management packages defined in the Ethernet Standard 802.3 Clause 30 for the
managed objects oMacEntity and oPauseEntity.
attributes only applicable to the IP core; other objects and attributes are derived from
your application or higher layers.
3–38.
Access
lists the resources available to implement the IEEE 802.3 mandatory
RW
RW
RW
RW
WC
Line loopback enable. Set to 1 to loopback the receiver traffic onto the
transmitter path.
To get correct loopback frames, you should first stop transmitting data, put
the IP core into line loopback mode and then resume transmission.
Broadcast filtering enable. 0 lets the receive broadcast frames through; 1
filters them out.
Insert one CRC error in the next transmit frame.To generate fault, set to 1. An
error is inserted in the next packet or possibly the second packet after the bit
is set due to latency to propagate the error. The bit self clears.
Disable FIFO pause. When set to 1, the receiver FIFO buffer does not trigger
the generation of pause frames on the transmitter path. Otherwise, pause
frames are triggered depending on thresholds.
Self-clearing counter reset command. Setting this bit to 1 clears the statistics
counters. This bit is automatically cleared when the counter reset sequence is
completed.
Table 3–16 on page 3–32
Description
“Command_Config Register” on
Table 3–19
and the statistics group
© July 2010 Altera Corporation
describes objects and
Register Descriptions